Configuring Bit Memory and Local Data Stack Allocation in SIMATIC PCS 7 S7-400 Controllers

In SIMATIC PCS 7 S7-400 and CPU 410 systems, memory allocation is structured across load memory, work memory, system memory (bit memory M, timers, and counters), and the local data stack (L stack). Configuring bit memory requires understanding Siemens big-endian byte-packing, where memory word MW0 comprises high byte MB0 and low byte MB1. Local data stack sizing is configured per priority class in CPU Hardware Configuration to prevent execution errors, while modern PCS 7 continuous control standardizes on instance data blocks rather than global bit memory.

Memory Architecture of SIMATIC S7-400 and CPU 410 Controllers

SIMATIC S7-400 automation stations partition controller memory into distinct physical and logical areas:
* Load Memory: Stores the complete compiled user program including symbols, comments, and system configuration. It can be internal RAM or extended via Flash/RAM memory cards.
* Work Memory: High-speed RAM partitioned into code work memory (executable instructions) and data work memory (data blocks and instance DBs).
* System Memory: Contains process image input (PII), process image output (PIQ), bit memory (Merker M area), timers (T), and counters (C).
* Local Data (L Stack): Dynamic scratchpad memory allocated to temporary variables (TEMP) within function blocks (FB), functions (FC), and organization blocks (OB) during active execution.

Bit Memory Structure and Endianness in STEP 7

The Merker (M) memory area operates on a byte-oriented byte-addressable matrix. SIMATIC S7 controllers utilize Motorola big-endian data representation:
* Bit (BOOL): Addressed as M <byte>.<bit>, e.g., M1.0 is bit 0 of memory byte 1.
* Byte (BYTE/CHAR): 8 contiguous bits (MB0 = M0.0 to M0.7).
* Word (WORD/INT): 16 contiguous bits comprising two bytes. MW0 consists of MB0 (Most Significant Byte, containing M0.7 down to M0.0) and MB1 (Least Significant Byte, containing M1.7 down to M1.0). Consequently, setting MW0 = 1 sets bit M1.0 to TRUE, not M0.0.
* Double Word (DWORD/DINT/REAL): 32 contiguous bits comprising four bytes. MD0 consists of MB0 (MSB), MB1, MB2, and MB3 (LSB).

Configuring Priority Class Local Data (L Stack) in HW Config

Each cyclic, diagnostic, and time-interrupt organization block (such as OB1, OB32, OB35, OB82, OB86) executes within a specific priority class that requires dedicated local data space:
1. Open SIMATIC Manager and double-click the Hardware object for the target S7-400 station.
2. Double-click the CPU in the rack to open Properties - CPU.
3. Select the Memory (or Cycle/Clock Memory) tab.
4. Locate the Local Data allocation table. Each priority class (from 1 to 29) has an assigned local data quota in bytes (default 256 or 512 bytes per priority class).
5. If deeply nested CFC subroutines or complex APL library blocks cause local data overflow (triggering CPU STOP with Event ID 16#4521), increase the local data quota for the affected priority class (e.g., from 512 bytes to 1024 or 2048 bytes).
6. Verify that the sum of local data across all priority classes does not exceed the total local data capacity of the CPU hardware specification.
7. Save and compile HW Config, then download hardware changes to the controller during a scheduled maintenance stop.

PCS 7 Engineering Practice: CFC Data Blocks vs. Global Merkers

In classical STEP 7 PLC programming, global bit memory (M) is frequently used for internal flags. In SIMATIC PCS 7, the use of global Merker memory is strongly discouraged for standard process automation:
* Integrity of Instance DBs: Continuous Function Chart (CFC) assigns unique instance data blocks (DBs) for every block placed on a sheet. This guarantees encapsulated state memory without risk of address collision.
* AS-OS Compilation: Block inputs and outputs defined in instance DBs with the S7_m_c attribute are automatically compiled into WinCC OS tags. Global bit memory does not automatically generate structured APL OS tags.
* Redundancy and Bumpless Transfer: In redundant AS pairs (H systems), instance data block contents are synchronized across fiber-optic sync links during each execution cycle. Global M memory synchronization requires specialized handling.

Verification

In SIMATIC Manager, open Target System -> Diagnostic/Setting -> Module Information.
Select the Memory tab to observe current and peak usage for work memory and local data.
Select the Performance Data tab to confirm the maximum configured local data per priority class.
In CFC, switch to dynamic test mode to verify that block interconnections resolve to valid data block addresses rather than overlapping bit registers.

Limitations and Operational Precautions

Modifying CPU local data stack parameters in HW Config requires downloading the system data blocks (SDB), which requires putting the automation station in STOP mode.
Exceeding the maximum local data capacity of the CPU prevents compilation of the hardware configuration.
Direct manipulation of bit memory within CFC charts via raw address connectors (M0.0) can cause cross-reference gaps and unexpected signal overwrites during delta compilations.

Engineer FAQ

What happens when an organization block exceeds its allocated local data stack?
The CPU calls organization block OB85 (priority class error). If OB85 is not programmed or if stack overflow corrupts system pointers, the controller transitions to STOP mode with Event ID 16#4521.
How can I determine the exact local data requirement of a CFC chart program?
In SIMATIC Manager, select Options -> Reference Data -> Filter, and choose Local Data. The cross-reference table displays the exact local data consumption of each OB call tree.
Can I increase the bit memory area of an S7-400 CPU?
No, the size of the bit memory area (e.g., 8 KB or 16 KB) is fixed by the CPU hardware firmware architecture and cannot be expanded by configuration.
Why is setting MW0 = 1 making M1.0 true instead of M0.0?
SIMATIC S7 uses big-endian byte order. In a 16-bit word, the byte with the lower address (MB0) is the most significant byte, and the byte with the higher address (MB1) is the least significant byte.
Does CPU 410-5H share the same local data structure as classical S7-400 CPUs?
Yes, CPU 410-5H partitions local data across priority classes in HW Config, but offers dynamic internal stack sizing and significantly larger default buffers (up to 64 KB total).
How does local data differ from temporary (TEMP) variables in an SCL block?
Temporary variables declared under VAR_TEMP are physically stored in the local data stack and lose their values immediately when block execution ends.
Can WinCC read S7 bit memory directly?
Yes, WinCC can address bit memory tags using the S7 protocol (M, MB, MW, MD), but this bypasses the standard PCS 7 APL tag compilation workflow.
What is the recommended local data setting for OB35 in PCS 7 APL projects?
Typical PCS 7 APL configurations allocate between 1024 and 4096 bytes of local data to priority class 12 (OB35) to accommodate nested channel drivers and control loops.
Does saving and reorganizing a STEP 7 project change local data allocation?
No, saving and reorganizing compacts database storage on the Engineering Station; it does not alter controller memory allocation parameters in HW Config.
Are Merker flags cleared during a warm restart?
Non-retentive Merker bytes are cleared to 0 during a warm restart (CRST), whereas retentive Merker bytes defined in CPU properties retain their states.

Technical References

SIMATIC S7-400 CPU Data Reference Manual (A5E00850745)
SIMATIC PCS 7 Engineering System Manual (V9.0 / V9.1)
SIMATIC STEP 7 V5.6 Programming with STEP 7 Manual
Siemens Industry Online Support Entry: Local Data Requirement in S7-400 (Entry ID 298370)

Related Tags

PCS 7, S7-400, CPU 410, Memory Architecture, Bit Memory, Local Data Stack, L Stack, Big-Endian, Hardware Configuration, CFC

Configuring Bit Memory and Local Data Stack Allocation in SIMATIC PCS 7 S7-400 Controllers