Configuring First-In Detection (Feature Bit 31) and Interlock Diagnostics in SIMATIC PCS 7 APL

In SIMATIC PCS 7 Advanced Process Library (APL), the First-In signal output (FirstIn / FirstIn1) of interlock blocks (Intlk02, Intlk04, Intlk08, Intlk16) remains inactive (stuck at 0) until Feature Bit 31 ('Activate First-in detection') is set to TRUE in the Feature parameter. By default, Feature Bit 31 is 0 (disabled) to conserve controller processing overhead. Once Feature.Bit31 is enabled and the block is reset via RstLi or the operator faceplate, the block captures and latches the exact input pin that triggered the trip condition.

APL Interlock Functionality and the First-In Mechanism

In continuous process automation, multiple trip signals frequently occur in rapid succession during an abnormal shutdown event. For example, when a slurry pump trips, low flow, high discharge pressure, and motor overload alarms may all activate within a few hundred milliseconds. Determining which fault occurred first (the root cause) is vital for plant safety and rapid recovery.

The SIMATIC PCS 7 Advanced Process Library provides dedicated interlock blocks (Intlk02, Intlk04, Intlk08, and Intlk16) equipped with an intelligent 'First-in' detection algorithm. When multiple interlock inputs fail, the block identifies the initial trip condition and indicates it via the FirstIn output and on the WinCC APL interlock faceplate.

The Role of Feature Bit 31: Enabling First-In Recording

A pervasive engineering misconception is that First-in detection operates out-of-the-box simply by connecting input signals. In APL V8.0, V8.1, V8.2, and V9.0+, all interlock blocks require explicit activation through the block's Feature byte array.

Specifically, Feature Bit 31 (Activate First-in detection / First-in signal recording) must be set to 1:

Feature.Bit31 = TRUE

When Feature.Bit31 = FALSE (the Siemens factory default), the internal first-in latching evaluation is bypassed entirely. The block continues to calculate the combined logical output (Out), but the FirstIn output pin remains permanently 0 (or hexadecimal 16#00), and the interlock faceplate cannot display the flashing root-cause trip icon.

Operating Philosophy: Latching, Faceplate Visualization, and Reset Logic

Once Feature Bit 31 is active, the first-in detection functions according to the following operational rules:

Signal Latching: When all interlock inputs are healthy (logic 1 for active-high interlocks) and one input fails (transitions to 0), the block immediately latches that input index into FirstIn. Even if subsequent inputs fail 10 ms later, FirstIn retains the original trip source.
Reset Requirements: The first-in status remains latched even if the faulted input returns to healthy. It can only be cleared when all inputs are healthy again AND a reset pulse is applied via RstOp (operator faceplate button) or RstLi (interconnection).
Interaction with Feature Bit 29 and 30: Feature Bit 29 ('Apply output value in substitution mode') and Feature Bit 30 ('Define reset behavior') determine whether operator authorization is required to clear first-in flags before drive restart.

Engineering Configuration Procedure in CFC

To configure First-In detection on an APL interlock block:

Open CFC Chart: Locate the interlock block (e.g., Intlk04) in the Continuous Function Chart.
Open Block Properties: Double-click the block or right-click and select Object Properties.
Navigate to Feature Parameter: Locate the Feature input structure. Click the expand button or open the bitmask dialog.
Enable Bit 31: Set Bit 31 (Activate First-in detection) to 1 (TRUE). Save the block properties.
Configure Reset Logic: Connect an operator reset command or plant startup pulse to RstLi (with RstLi.ST = 16#80), or allow operator reset via faceplate by configuring OS_Perm.
Compile and Download Changes: Execute a CFC Delta Compile and Delta Download to the target CPU. The first-in engine becomes immediately active without halting the automation system.

APL Interlock Block Family Feature Comparison

The following table summarizes the capabilities and pin assignments of the APL interlock family:

Block TypeNumber of InputsInversion AvailableFirst-In ParameterFirst-In ActivationPrimary ApplicationIntlk022 Inputs (In01..02)Yes (InvIn01..02)FirstIn1 (DWord)Feature.Bit31 = TRUESimple permissive / run interlock pairsIntlk044 Inputs (In01..04)Yes (InvIn01..04)FirstIn1 (DWord)Feature.Bit31 = TRUEPump, fan, and standard valve interlocksIntlk088 Inputs (In01..08)Yes (InvIn01..08)FirstIn1 (DWord)Feature.Bit31 = TRUECompressor protection and unit trip loopsIntlk1616 Inputs (In01..16)Yes (InvIn01..16)FirstIn1, FirstIn2Feature.Bit31 = TRUEComplex burner or reactor safety clusters

Verification

Verify First-In operation through the following test sequence:

Open the CFC chart online and monitor the Intlk04 block.
Force all inputs In01 through In04 to 1 (healthy). Verify Out = 1 and FirstIn1 = 16#00000000.
Transition In02 to 0 (trip). Verify that Out changes to 0 and FirstIn1 immediately reflects bit 2 (16#00000002).
While In02 remains 0, transition In03 to 0. Confirm that FirstIn1 remains strictly locked at 16#00000002.
Open the WinCC APL faceplate for the downstream drive (e.g., MotL). Open the Interlock preview window and verify that Input 2 displays the distinctive first-in alarm icon.

Limitations and Operational Precautions

Consider these operational rules when implementing APL interlocks:

Cycle Execution Window: The resolution of First-In detection is bound to the execution cycle of the OB in which the interlock block is scheduled (e.g., 100 ms in OB35). If two physical inputs trip within the exact same 100 ms scan cycle, the block evaluates the input with the lowest pin number (In01 before In02) as the first-in.
Cascade Cascading Interlocks: When cascading multiple interlocks (e.g., an Intlk08 output feeding into an Intlk04), first-in latching must be reset in reverse hierarchy; otherwise, upstream first-in indicators will remain latched after parent resets.
Signal Status Integration: Ensure all inputs supply good signal status (16#80). If an input has bad status (16#00), APL blocks treat it according to Feature.Bit23 ('Evaluate signal status of interlock signals').

Engineer FAQ

What is the data type of FirstIn1 on Intlk08 and Intlk16?

FirstIn1 is a 32-bit DWORD where individual bits represent input pins (Bit 0 = In01, Bit 1 = In02, etc.). On Intlk16, FirstIn2 handles inputs 9 through 16.

How does First-In display on the WinCC APL faceplate?

In the APL interlock faceplate, the input that triggered the first-in condition is highlighted with a flashing icon and distinctive color border, distinguishing it from subsequent cascaded trips.

What happens if Feature Bit 31 is enabled while an interlock is already tripped?

The block evaluates the current input states on the next execution cycle. If already tripped, it may latch the first active low input detected in numerical pin order.