Connecting Physical I-O Signals to PCS 7 APL Structured Pins in CFC Using StruDiOu and StruAnOu

In SIMATIC PCS 7 Continuous Function Chart (CFC) editor, when an engineer attempts to connect a hardware input address (such as I0.0) or symbol directly to an Advanced Process Library (APL) block input using 'Interconnection to Address' and receives an empty dialog or type conflict error, the issue arises because APL block technological pins are structured data types (Struct containing Value and ST) rather than elementary BOOL or REAL types. Standard PCS 7 DCS architecture requires connecting physical I/O through APL channel driver blocks (Pcs7DiIn or Pcs7AnIn). However, if direct address interconnection without channel drivers is desired for auxiliary logic or testing, you must insert an APL structure conversion block—such as StruDiOu (FC 378) for digital signals or StruAnOu (FC 376) for analog signals—to encapsulate the elementary hardware address and signal status into a valid APL structure.

Executive Summary

Engineers transitioning from classical STEP 7 (LAD/FBD/STL) or TIA Portal to SIMATIC PCS 7 often attempt to connect physical I/O addresses (I0.0, IW512) directly to control block pins in the CFC editor. In the Advanced Process Library (APL), all process variables are modeled as composite technological structures containing both the primary engineering value and a NAMUR NE107 signal status quality code (ST). Because CFC enforces strict compile-time data type checking, connecting an elementary boolean bit to a structured input pin fails. Understanding the distinction between classical PLC I/O wiring, APL channel drivers, and structure converter functions ensures robust and standardized logic design.

Architecture and Fundamental Mechanics

The data typing and interconnect mechanics of PCS 7 APL operate on rigorous structural definitions:

The APL Technological Structure Standard:
* In classical STEP 7, a digital input is a simple elementary data type: BOOL (1 bit).
* In PCS 7 APL, inputs on technological blocks (e.g., Intlk02.In01, MotL.FbkRun, VlvL.FbkOpen) are declared as structures:
- Struct:
- .Value : BOOL (Process value)
- .ST : BYTE (Signal Status quality code, e.g., 16#80 for Good, 16#60 for Simulation, 16#28 for Bad)
- Analog inputs are similarly structured with .Value : REAL and .ST : BYTE.
The CFC Type Enforcement Engine:
* When selecting Interconnection to Address in CFC, the editor queries the Symbol Table and filter addresses matching the exact data type of the target pin.
* Because physical hardware addresses in the Symbol Table are declared as elementary BOOL or WORD/INT, they do not match the Struct type of the APL pin, resulting in an empty selection dialog or an incompatible type rejection.
Architectural Resolution Paths:
* Path 1: Standard DCS Channel Driver Pattern (Best Practice):
- Instantiate Pcs7DiIn (FB 1867) or Pcs7AnIn (FB 1869).
- Connect the hardware address (I0.0) to the channel driver's elementary input pin PV_In.
- Connect the channel driver's structured output pin PV_Out to the technological block pin (Intlk02.In01).
- The PCS 7 module driver generator automatically monitors hardware health, wire breaks, and manages signal quality.
- Path 2: Structure Converters (Direct Connections):
- Where full channel drivers are not required (e.g., internal flags or simplified auxiliary signals), use APL structure conversion functions:
- StruDiOu (FC 378, Convert BOOL to Digital Structure).
- StruAnOu (FC 376, Convert REAL to Analog Structure).
- Connect the physical address to In, configure ST = 16#80 (Good), and route Out to the technological block.

Step-by-Step Implementation Procedure

Follow these procedures to connect physical I/O signals to APL blocks in CFC:

Method A: Using Standard Channel Drivers (Recommended DCS Workflow):
* In SIMATIC Manager HW Config, ensure all I/O cards are addressed and given symbolic names in the Symbol Table (e.g., BC02_M_AUTO mapped to I0.0).
* In CFC editor, open the block catalog under Libraries > PCS 7 AP Library > Channel.
* Drag Pcs7DiIn (for digital inputs) or Pcs7AnIn (for analog inputs) into the chart.
* Right-click input pin PV_In on Pcs7DiIn and select Interconnection to Address....
* Select symbol BC02_M_AUTO from the populated symbol list and click OK.
* Connect the output pin PV_Out of Pcs7DiIn directly to the target APL block input (e.g., Intlk02.In01).
* During CFC compilation, ensure Generate module drivers is checked.
Method B: Using Structure Converters (StruDiOu / StruAnOu):
* If connecting an address without generating module drivers:
* In the CFC block catalog, navigate to Libraries > PCS 7 AP Library > Structure.
* Drag StruDiOu (FC 378) into the CFC chart.
* Right-click input pin Value on StruDiOu and select Interconnection to Address....
* The elementary address I0.0 or symbol BC02_M_AUTO will appear in the list; select it and confirm.
* Check the input pin ST on StruDiOu; ensure it is set to 16#80 (representing Good process quality).
* Connect output pin Out of StruDiOu to the structured input pin of your technological block (e.g., Intlk02.In01).
Method C: Deconstructing Structures (StruDiIn / StruAnIn):
* If you need to read a boolean value out of an APL block and write it to a physical output coil (Q0.0):
* Drag StruDiIn (FC 377) into the chart.
* Connect the APL structured output to StruDiIn.In.
* Connect StruDiIn.Value via Interconnection to Address... to output coil Q0.0.

Verification

In CFC editor, switch to Test Mode (online). Verify that toggling the physical field switch or forcing I0.0 updates the Value pin. Confirm that the structured connection displays live green status in CFC and that the downstream block (Intlk02) evaluates the input without asserting a bad status fault (ST = 16#80).

Limitations and Operational Precautions

Bypassing channel drivers with StruDiOu avoids consuming driver block instances, but eliminates automated hardware diagnostics (wire break detection, module failure alarms, and HART status updates) provided by the PCS 7 Basis Library. Always use standard Pcs7DiIn/Pcs7AnIn channel drivers for primary safety-related, critical control, and field instrumentation signals.

Engineer FAQ

Why did 'Interconnection to Address' show an empty list for my block input?

The block input expects an APL structure (Struct containing Value and ST), whereas physical I/O addresses in the symbol table are elementary BOOL or WORD types.

What is the function of StruDiOu (FC 378)?

StruDiOu packages an elementary BOOL input and a signal status BYTE into a standard APL digital structure for interconnection to APL block inputs.

What is the difference between StruDiOu and Pcs7DiIn?

StruDiOu is a lightweight converter function that simply formats data; Pcs7DiIn is a complete channel driver block that interfaces with Basis Library diagnostic blocks for hardware fault monitoring.