Developing Custom SCL Function Blocks with Multi-Instance Timers (TIMER_P) in SIMATIC PCS 7

In SIMATIC PCS 7, developing custom function blocks in S7-SCL that require timing logic requires instantiating the PCS 7 system timer block TIMER_P (FB5 from CFC Library) or standard IEC timers as multi-instances within the VAR declaration. Calling global S5 timers (T0..T255) in reusable SCL blocks is strictly prohibited in PCS 7, as global timer numbers collide across multiple chart instances. Declaring TIMER_P as a multi-instance variable embeds the timer state directly into the parent block's instance Data Block (DB), ensuring reusability, memory isolation, and seamless CFC integration.

Why Global S5 Timers Fail in SIMATIC PCS 7

In standard STEP 7 ladder programming, engineers frequently use global timers (such as T 1 or S_ODT). In SIMATIC PCS 7, this approach causes critical runtime defects:
* Global Resource Collisions: S7-400 CPUs have a limited pool of global timers (typically 256 to 512). If a custom motor FB uses T 10, instantiating the motor block 50 times in CFC results in all 50 motors overwriting the same timer memory!
* Loss of Reusability: PCS 7 relies on modular, object-oriented engineering. Every block must be completely self-contained.
* CFC Interruption Safety: Global timers are not tied to CFC sampling times and cannot be properly scaled when moving blocks between cyclic interrupt organization blocks (e.g. OB32 vs OB35).

Declaring and Calling Multi-Instance TIMER_P in S7-SCL

The official PCS 7 solution is to declare TIMER_P (FB5) as a multi-instance within the static variable declaration of the parent Function Block:
1. Declaration: In the VAR ... END_VAR section, declare the timer as an instance of TIMER_P.
2. Execution: Call the timer inside the execution body, passing time values (TIME) and control inputs (BOOL).
3. Instance Data Block Integration: When the parent FB is placed in a CFC chart, STEP 7 automatically creates an instance DB containing the timer's internal state variables, eliminating all external timer dependencies.

SCL Motor Controller Implementation Example

The following production-ready S7-SCL code demonstrates a custom motor controller (FB10) with start/stop interlocks and a run-feedback watchdog timer using TIMER_P:

FUNCTION_BLOCK FB10
TITLE = 'Motor_Controller'
{ S7_m_c := 'true'; S7_tasklist := 'OB100' }
AUTHOR : 'EngTeam'
FAMILY : 'USER_LIB'

VAR_INPUT
    Start     : BOOL;         // Start command (pulse or latch)
    Stop      : BOOL;         // Stop command (active high)
    Feedback  : BOOL;         // Contactor run feedback
    TripTime  : TIME := T#5s; // Watchdog trip delay
    Reset     : BOOL;         // Fault reset command
END_VAR

VAR_OUTPUT
    Q_Run     : BOOL;         // Contactor drive output
    Q_Fault   : BOOL;         // Feedback fault alarm
END_VAR

VAR
    Run_State : BOOL;         // Internal run latch
    Timer_Fb  : TIMER_P;      // Multi-instance PCS 7 timer (FB5)
END_VAR

BEGIN
    // Logic: Start / Stop control
    IF Stop OR Q_Fault THEN
        Run_State := FALSE;
    ELSIF Start THEN
        Run_State := TRUE;
    END_IF;

    Q_Run := Run_State;

    // Call Multi-Instance TIMER_P for Run Feedback Watchdog
    Timer_Fb(
        I0   := (Run_State AND NOT Feedback), // Run commanded but no feedback
        MODE := 0,                            // Mode 0: On-Delay pulse
        TI   := TripTime                      // Delay duration
    );

    // If watchdog timer expires, latch fault
    IF Timer_Fb.Q THEN
        Q_Fault := TRUE;
    ELSIF Reset THEN
        Q_Fault := FALSE;
    END_IF;

END_FUNCTION_BLOCK

Timer Implementation Architectural Comparison

Compare the timer mechanisms available in SIMATIC S7 and PCS 7:

Timer TypeImplementation MethodMulti-Instance SafePCS 7 ReusabilityOS IntegrationGlobal S5 Timer (T_ODT)Hardware timer registersNo (Single global instance)Prohibited in PCS 7NoneStandard IEC Timer (SFB4 TON)Standard IEC multi-instanceYesSupportedManualPCS 7 Timer (TIMER_P FB5)CFC Library system blockYesNative PCS 7 standardAutomatic timebase scalingAPL Timer (TimerP FB1810)Advanced Process LibraryYesRecommended for modern APLNative APL faceplate binding

Verification

To confirm that the custom SCL block functions accurately:
1. In S7-SCL, execute File -> Compile; verify that zero errors and zero warnings are generated.
2. In SIMATIC Manager, open a CFC chart and insert FB10 from the block catalog.
3. Verify that the block appears with all inputs (Start, Stop, Feedback, TripTime) and outputs (Q_Run, Q_Fault).
4. Switch CFC to Test Mode online; force Start := TRUE without providing Feedback.
5. Verify that Q_Run energizes, and after the 5-second TripTime elapses, Q_Fault trips and de-energizes Q_Run.

Limitations and Operational Precautions

Never use MODE := 2 (Off-Delay) or custom pulse modes without verifying that the input pulse length satisfies the minimum CFC sampling time. When updating a custom SCL block with new multi-instance timers, the block interface changes, requiring a CPU compile. If interface changes alter the instance DB size, a CPU download in STOP mode may be required if memory cannot be reorganized online.

Engineer FAQ

Where is TIMER_P located in the STEP 7 library catalog?

It is located in CFC Library -> ELEMENTA -> IMPULS -> TIMER_P (FB5).

Can I use IEC timer SFB4 (TON) instead of TIMER_P?

Yes, SFB4 is fully multi-instance capable and supported, but TIMER_P is preferred in PCS 7 because it includes specific mode inputs and CFC task-sampling adaptation.

Why does S7-SCL error with 'Unknown identifier TIMER_P' during compilation?

FB5 (TIMER_P) must be present in the offline S7 Program Blocks folder before compiling the SCL source. Copy FB5 from the CFC Library to the project blocks folder.