Documenting Sequential Function Charts (SFC) in SIMATIC PCS 7 - IEC 61131-3, IEC 60848 GRAFCET, and ISA-88 Standards

When creating a Control Logic Diagram or functional specification for SIMATIC PCS 7 applications implemented in Sequential Function Charts (SFC) and Continuous Function Charts (CFC/FBD), engineering documentation should be structured around three internationally recognized standards. Use IEC 60848 (GRAFCET) for vendor-neutral functional sequence specifications (steps, transitions, and action qualifiers) before code generation; align phase state logic with ANSI/ISA-88 (IEC 61512) state transition models for batch and procedural automation; and utilize ANSI/ISA-5.2 (Binary Logic Diagrams) or Cause & Effect matrices for interlocking and permissive logic. In PCS 7, SFC natively executes the IEC 61131-3 graphical state engine while complying directly with ISA-88 operating states.

Standardization Hierarchy for Process Control Logic Documentation

Documenting process automation software requires clear separation between functional conceptual specification (what the process must do) and target software implementation (how the controller executes the code). In SIMATIC PCS 7, sequential logic is implemented using SFC (Sequential Function Chart) and continuous interlocking/analog control is implemented using CFC (Continuous Function Chart / FBD).

In industrial projects across chemical, pharmaceutical, oil & gas, and food & beverage sectors, engineers must align documentation with recognized standards rather than inventing proprietary diagramming conventions. A rigorous engineering documentation framework leverages a three-tier hierarchy:

Functional Specification Tier (IEC 60848 GRAFCET): Vendor-neutral representation of sequence steps, transitions, directional branches, and action qualifiers understood by process technologists, chemical engineers, and validation teams.
Procedural Control Hierarchy Tier (ANSI/ISA-88 / IEC 61512): Architectural state models governing equipment modules, phases, and recipe operations (Starting, Running, Paused, Holding, Aborting).
Discrete Interlock Tier (ANSI/ISA-5.2 / Logic Matrix): Formal boolean logic representations (AND, OR, NOT, Flip-Flops) defining safety permissives, process interlocks, and emergency trip matrices.

IEC 60848 (GRAFCET) vs IEC 61131-3 SFC Implementation

A common point of confusion is the distinction between IEC 60848 and IEC 61131-3:

IEC 60848 (GRAFCET) is an international specification standard for sequential function charts. It is purely descriptive and platform-independent. It defines graphic elements (initial steps, single steps, transitions, directed links, alternative and parallel branches) and action types (continuous actions, actions with assignment, time-delayed actions, and stored events). Process engineers write the Functional Design Specification (FDS) using IEC 60848 so that it can be reviewed and approved prior to PLC programming.
IEC 61131-3 (SFC Programming Language) is an international programming language standard for programmable logic controllers. SIMATIC PCS 7 SFC is an industrial implementation of IEC 61131-3. While based on GRAFCET concepts, PCS 7 SFC introduces controller-specific execution rules: cyclic scanning, runtime group scheduling (OB32–OB35), step execution phases (Initialization, Cyclic, Termination), and direct CPU memory addressing.

ISA-88 Procedural Control Models in PCS 7 SFC Types and Instances

For batch and multi-phase processes, documentation must follow ANSI/ISA-88.01 (IEC 61512-1). SIMATIC PCS 7 SFC natively incorporates the ISA-88 state transition model through SFC Types:

Equipment Phases (EPH) and Equipment Modules (EM) are modeled as reusable SFC Types with predefined state machines.
The standard ISA-88 state model includes transient and quiescent states: Idle, Starting, Running, Completing, Completed, Pausing, Paused, Holding, Held, Resuming, Restarting, Stopping, Stopped, Aborting, and Aborted.
When authoring the Control Logic Diagram, each sequence should be documented as a state transition matrix showing which operational commands (Operator or Recipe) or process conditions trigger state transitions (e.g., transition from Running to Holding upon loss of cooling water pressure).

ISA-5.2 Binary Logic Diagrams and Cause & Effect Matrices for CFC Interlocks

While SFC manages sequential flow, continuous interlocking logic (such as motor permissives, valve protection, and trip conditions) is implemented in CFC using APL interlock blocks (Intlk02, Intlk04, Intlk08, Intlk16).

ANSI/ISA-5.2 Standard: Defines binary logic diagrams for process operations using standard logic symbols (AND gates, OR gates, time delays, and memory latches). This standard is ideal for documenting trip circuits and safety interlocks.
Cause & Effect (C&E) Matrix: An industry-preferred alternative to raw logic diagrams. Rows list initiating process causes (e.g., PIT-101 Pressure > 5.0 bar), and columns list automated protective effects (e.g., Close XV-102, Stop P-101).
In PCS 7, the SIMATIC Safety Matrix or PCS 7 Logic Matrix tool allows engineers to directly import C&E matrices into the engineering system, automatically compiling them into certified CFC interlock logic.

Comparative Standard Matrix: Process Control Documentation Frameworks

The following table summarizes the standards, application domains, and PCS 7 engineering equivalents for control logic documentation:

Standard / FrameworkPrimary PurposeGraphic / Structural ElementsTarget AudienceDirect PCS 7 EquivalentIEC 60848 (GRAFCET)Sequential SpecificationSteps, Transitions, Action QualifiersProcess & Chemical EngineersSFC Chart StructureIEC 61131-3 (SFC/FBD)PLC Programming SyntaxSFC Networks, Function Blocks, IO PinsAutomation EngineersPCS 7 SFC & CFC EditorsANSI/ISA-88 (IEC 61512)Batch & Procedural ControlState Transition Models, Phases, RecipesPlant Operations & ValidationPCS 7 SFC Types / SIMATIC BATCHANSI/ISA-5.2Binary Logic SpecificationLogic Gates (AND/OR), Memory Flip-FlopsSafety & Electrical EngineersAPL Interlock Blocks (Intlk08)VDI/VDE 3682Formalized Process DescriptionTechnical Operations, Material FlowsSystem Designers & PlannersPlant Hierarchy & P&ID MappingISO 10628 / ISA-5.1Piping & Instrumentation (P&ID)Instrument Bubbles, Piping Lines, ValvesProcess Designers & OperatorsPCS 7 Process Graphics (*.pdl)

Structuring an Audit-Compliant Functional Design Specification (FDS)

To create a comprehensive Control Logic Diagram document for a PCS 7 project, structure the document into the following systematic sections:

System Overview and Scope: Executive summary defining the physical equipment, design criteria, and automation boundaries.
Physical Hierarchy and Tag Naming Conventions: Plant hierarchy breakdown (Plant -> Unit -> Equipment Module -> Control Module) aligned with ISA-88 and KKS or custom tagging standards.
Continuous Control & Interlocking Specifications (ISA-5.2 / C&E Matrices):
- Motor/valve permissives, interlocks (Intlk02, Intlk08), and bypass rules.
- Analog scaling, alarm limit tables, and PID loop controller narratives.
Sequential Control Specifications (IEC 60848 GRAFCET Diagrams):
- Step number, step description, and execution duration limits.
- Actions executed during step entry (Initialization), continuous execution (Cyclic), and step exit (Termination).
- Transition conditions with explicit boolean logic equations (e.g., T1: TT_101.PV > 85.0 AND P_101.Running).
State Transition Tables (ISA-88 State Models):
- Transition conditions for Holding, Pausing, Stopping, and Aborting.
- Recovery procedures from abnormal states (e.g., Held -> Resuming -> Running).
Operator Interface & Security Definitions: Faceplate access rights, manual override boundaries, and alarm priority assignments.

Verification

Verify the documentation against the PCS 7 implementation using the following methodology:

Traceability Matrix: Conduct a bidirectional cross-check comparing each GRAFCET transition condition against the compiled SFC transition logic in CFC/SFC Editor.
State Model Validation: In S7-PLCSIM, load the SFC Type instance, trigger state change requests (Pause, Hold, Abort), and confirm that the controller transitions exactly as specified in the ISA-88 state transition diagram.
Interlock Verification: Test every row of the Cause & Effect matrix by simulating trip inputs in CFC Test Mode and verifying that actuators trip to their designated fail-safe states within the specified process safety time.

Limitations and Operational Precautions

GRAFCET Execution Ambiguities: While IEC 60848 allows multiple active steps in parallel branches, PCS 7 SFC imposes strict cycle-based execution rules. Ensure parallel branch convergences always have unambiguous transition conditions to avoid sequencer stalling.
SFC Step Processing Phases: Unlike classic PLCs that execute actions continuously while a step is active, PCS 7 SFC distinguishes between Initialization, Processing, and Termination phases. Documentation must explicitly specify in which phase an action occurs.
Regulatory Validation: In FDA-regulated (GMP) life science environments, changes to the FDS require rigorous change control and formal qualification protocols (DQ, IQ, OQ) under GAMP 5 guidelines.

Engineer FAQ

Can I generate the Control Logic Diagram automatically from PCS 7?

Yes. In SIMATIC Manager, you can print the SFC charts directly or use DOCPRO to generate standardized documentation containing chart diagrams, cross-references, step actions, and transition logic. Furthermore, PCS 7 Logic Matrix can export Cause & Effect documentation directly.

What is the difference between an SFC Chart and an SFC Type in documentation?

An SFC Chart is an individual, non-reusable sequence instance programmed directly in a CFC chart. An SFC Type is a reusable template defined in the master library with formalized ISA-88 state logic, control strategies, and block inputs/outputs.

Why should process engineers use IEC 60848 instead of vendor-specific SFC documentation?

IEC 60848 provides a vendor-neutral standard understood by non-programmers (process technologists, operators, mechanical designers). It allows process logic to be thoroughly validated and approved before committing engineering hours to controller programming.

How are timer functions documented in GRAFCET transitions?

Under IEC 60848, timers in transitions are represented as t / Xi / d (where Xi is the step number, d is the duration, and t is the time elapsed since step activation), which maps directly to the step run time StepName.TI in PCS 7 SFC.

Is FBD (Function Block Diagram) identical to PCS 7 CFC?

No. While CFC utilizes function block graphical syntax similar to IEC 61131-3 FBD, CFC is a Continuous Function Chart editor supporting macro-structures, execution order run sequences, and inter-chart cross-references across multiple cyclic interrupt OBs.