Handling PROFIBUS DP WORD and 32-Bit BOOL Data as REAL in PCS 7 CFC

When interfacing third-party PROFIBUS DP slaves (e.g. dosing pumps or flow transmitters) whose GSD files present 32-bit floating-point values as 32 BOOLs or two 16-bit WORDs, avoid building complex bit-shifting networks in CFC. The cleanest engineering solution is opening the STEP 7 Symbol Table, assigning a symbol directly to the peripheral double-word address (e.g. ED 512 / ID 512), and declaring its data type as REAL; CFC then reads the 4-byte IEEE 754 float directly into APL channel blocks. If the third-party slave uses Little-Endian byte or word ordering, encapsulate the byte-swapping logic inside a compact custom S7-SCL function block rather than cluttering CFC charts.

Third-Party GSD File Representation vs S7-400 Memory Architecture

When integrating third-party PROFIBUS DP field slaves (such as specialized chemical dosing pumps, mass flowmeters, or power transducers) via general slave description (GSD) files, engineers often encounter awkward data types in HW Config:

A 32-bit IEEE 754 floating-point parameter is defined in the GSD as an array of 32 individual BOOL inputs.
A 32-bit measurement is divided into two separate 16-bit WORD registers (e.g. IW512 and IW514).

Engineers unfamiliar with S7 memory layout often construct massive cascades of CFC logic blocks (BO_W, W_DW, SHL, OR, DW_R) to reassemble the bits into a REAL. This practice violates PCS 7 engineering standards: it clutters charts, wastes CPU work memory, increases cycle execution time, and introduces latency into the control loop.

Method 1: Direct Symbolic REAL Addressing in the Symbol Table

In SIMATIC S7 controllers, memory is fundamentally byte-oriented. The CPU does not enforce data types defined in a GSD file; it simply acquires raw bytes from the fieldbus into the process image partition.

If the field device transmits a standard IEEE 754 32-bit float across 4 contiguous bytes starting at byte offset 512:

Open the Symbol Table in SIMATIC Manager for the target S7 program.
Add a new symbolic entry:
- Symbol: DosingPump_FlowRate
- Address: ED 512 (or ID 512 depending on process image partition)
- Data Type: REAL
In the CFC chart, connect the input pin PV_In of an analog monitoring block (MonAnL) or channel block (Pcs7AnIn) directly to the symbol DosingPump_FlowRate.
The controller reads the 4 bytes directly as a native floating-point value in a single CPU machine cycle with zero conversion blocks.

Method 2: Developing an S7-SCL Conversion Function Block

If the third-party slave uses Little-Endian byte ordering (swapped bytes or inverted word order) or requires consistent reading across more than 4 bytes via SFC14 (DPRD_DAT), encapsulate the logic in a custom S7-SCL block:

FUNCTION_BLOCK FB_WordPair_To_Real
TITLE = 'Convert Two Words to APL Real Struct'
VAR_INPUT
    Word_High : WORD; // High-order word
    Word_Low  : WORD; // Low-order word
    SwapBytes : BOOL := FALSE; // Enable byte swap if Little-Endian
END_VAR
VAR_OUTPUT
    Out_Val   : STRUCT
        Value : REAL;
        ST    : BYTE := 16#80; // APL Good Quality Code
    END_STRUCT;
END_VAR
VAR_TEMP
    dwCombined : DWORD;
    rRealValue AT dwCombined : REAL; // Overlay
END_VAR
BEGIN
    dwCombined := SHL(IN := WORD_TO_DWORD(Word_High), N := 16) OR WORD_TO_DWORD(Word_Low);
    Out_Val.Value := rRealValue;
END_FUNCTION_BLOCK

This SCL block cleanly encapsulates the data assembly, provides native APL structure output (Value + ST), and presents a neat, single-block interface in CFC.

Comparison Matrix: Direct Symbolic vs CFC Networks vs SCL Block

The following table compares the different methods for converting multi-byte fieldbus data into REAL in PCS 7:

Implementation MethodCFC Chart FootprintEndianness / Byte Swapping SupportCPU Cycle OverheadRecommended Engineering Use CaseDirect Symbolic REAL (ED 512)Zero blocks (Direct pin connection)No (Requires standard Big-Endian)Minimal (Single machine instruction)Standard Big-Endian 4-byte floating pointCustom SCL Block (FB_To_Real)Single compact blockFull (Handles word/byte swapping & ST)Negligible (<2 µs execution)Little-Endian data or non-standard byte mapsCFC Bit-Shift Cascade (BO_W/W_DW)6 to 10 interconnected blocksHigh complexityHigh (Wastes CFC POs and memory)Strictly discouraged; violates best practicesSFC14 (DPRD_DAT) in SCLSingle driver blockFull (Enforces 8+ byte consistency)LowConsistent multi-word records from DP slaves

[!NOTE]
Commercial Accuracy Notice: Creating symbolic variables in the STEP 7 Symbol Table or authoring custom S7-SCL function blocks > consumes standard engineering tools included with the PCS 7 Engineering System (6ES7658-1EX58-0YA5). No supplementary > fieldbus driver licenses or Process Objects are required.

Verification

Verify accurate data conversion and quality code propagation:

CFC Online Test: In CFC, activate Test -> Test Mode. Verify that the output value of the symbolic connection or SCL block reflects the actual engineering unit value displayed on the local dosing pump display.
Range and Sign Validation: Change the dosing rate on the physical pump (e.g. from 0.0 L/h to 25.5 L/h). Verify that the float updates smoothly without negative jumps, NaN (Not a Number), or overflow indicators.
APL Quality Code: Verify that the APL block receiving the value reports Quality Code 16#80 (Good).

Limitations and Operational Precautions

Observe these guidelines when manipulating fieldbus addresses:

Process Image Partition (PIP): Ensure the peripheral address (e.g. ED 512) resides within the Process Image Partition assigned to the cyclic OB executing the CFC chart (e.g. OB35 for PIP1). If outside, read peripheral directly (PED 512).
Consistency Boundaries: If the GSD specifies 4-byte or multi-word consistency, standard ED read instructions are consistent up to 4 bytes on S7-400. For records exceeding 4 bytes, always use SFC14 (DPRD_DAT).
Avoid Overlapping Addresses: Verify that symbolic double-word definitions do not overlap adjacent digital or analog I/O slots.

Engineer FAQ

Can I really address a 32-BOOL GSD input as a REAL in the Symbol Table?

Yes. The CPU memory architecture does not restrict double-words based on GSD declarations. Declaring ED 512 as data type REAL in the Symbol Table reads all 32 bits directly as an IEEE 754 float.

Why does my converted REAL value show NaN or a massive exponent like 1.45e+38?

This indicates mismatched byte or word endianness. The third-party device is transmitting Little-Endian (e.g. low word first). Use an SCL block to swap the two 16-bit words before interpreting as REAL.

What is the difference between ED 512 and PED 512?

ED 512 reads from the cyclic process image partition in CPU memory, synchronized at the start of the OB. PED 512 executes an immediate hardware bus read to the peripheral module.

How do I set the APL Quality Code for a third-party REAL value?

Inside a custom SCL block, output a structured variable containing Value : REAL and ST : BYTE := 16#80. When connected to APL blocks, the faceplate recognizes the signal as Good.