How to Connect Raw Data Block Booleans to APL Multi-Input Logic Blocks in PCS 7 CFC

In SIMATIC PCS 7 CFC, raw boolean tags from standard Data Blocks (DBs) cannot be connected directly to APL logic blocks (such as And04, And08, Or04, Or08 in the LogicDi folder) because APL blocks require structured data types containing both a boolean Value and a signal status byte (ST). To connect DB booleans, either expand standard elementary logic gates from the BIT_LGC folder by right-clicking the block and selecting 'Number of I/Os...', use the conversion block StruDiOu from the Convert folder to wrap the boolean into an APL structure, or expand the structured pin in CFC by clicking '+' to interconnect directly to the .Value element.

Data Type Incompatibility: Elementary BOOL vs APL Structured Signals

In SIMATIC PCS 7 CFC engineering, newly integrated automation engineers frequently encounter a frustrating barrier: a boolean tag located in a global Data Block (e.g., DB100.DBX0.0) can be connected easily to a 2-input AND gate in the BIT_LGC library, but dragging that same tag onto an And04 or Or08 block from the LogicDi folder displays a prohibited cursor (circle with a slash).

This occurs because PCS 7 enforces strict type checking:
* Elementary Data Types (BIT_LGC): Classic STEP 7 logic blocks (AND, OR, XOR) operate on basic IEC 61131-3 BOOL variables (1 bit: 0 or 1).
* APL Structured Data Types (LogicDi): All blocks in the Advanced Process Library (APL) utilize structured data types to propagate signal quality alongside process data. An APL digital input (such as In1 on And04) is defined as a STRUCT:
* Value : BOOL (the actual binary signal state)
* ST : BYTE (the signal quality status conforming to IEC 61804).
* A raw DB boolean lacks the ST byte, causing the CFC compiler to reject the direct connection to protect signal status integrity.

Method 1: Expanding Elementary BIT_LGC Logic Gates to Multiple Inputs

If your application only requires multi-input boolean logic without needing APL signal status propagation:

Insert Elementary Gate:
* Open the CFC chart.
* In the block catalog under Libraries > Standard Library > Blocks > BIT_LGC, drag an AND (or OR) block onto the chart.
Expand Number of Inputs:
* By default, the AND block displays only two inputs (In1 and In2).
* Right-click the AND block header and select Number of I/Os....
* In the dialog box, enter the desired number of inputs (from 2 up to 32 inputs).
* Click OK. The CFC editor expands the block dynamically, creating In3, In4, ..., In32.
Connect DB Booleans:
* Drag boolean variables from any global Data Block directly onto any of the expanded input pins. All connections are accepted without type mismatch errors.

Method 2: Converting Elementary Booleans with StruDiOu (Convert Library)

When the output of the boolean logic must feed directly into APL equipment blocks (such as VlvL.Intlock or MotL.Permit), the signal must carry a valid APL structure:

Insert StruDiOu:
* In the CFC block catalog, navigate to Libraries > PCS 7 AP Library > Blocks > Convert.
* Drag the block StruDiOu (FB1253 - Structure Digital Output) onto the chart.
Configure Conversion Inputs:
* Connect your DB boolean tag (e.g., DB100.DBX0.0) to StruDiOu.In.
* Configure parameter SubsST: Set to 16#80 (Good) to establish a valid quality code.
Interconnect to APL Logic Blocks:
* Connect StruDiOu.Out directly to And04.In1 or Or08.In2.
* Because StruDiOu.Out is an APL-compliant digital structure (Struct: Value, ST), the connection is accepted cleanly, and the APL block propagates 16#80 downstream.

Method 3: Expanding Structure Elements Directly in the CFC Editor

The fastest method to connect a raw DB boolean directly to an APL block without adding extra converter blocks is using sub-element expansion:

Locate the Structured Pin:
* On the And04 or Or08 block in CFC, locate the input pin (e.g., In1).
Expand the Structure:
* In the CFC editor, notice the small square plus icon (+) immediately to the left of the parameter name In1.
* Click the (+) icon. The parameter expands vertically, exposing its sub-elements:
- In1.Value (Data Type: BOOL)
- In1.ST (Data Type: BYTE)
Connect Raw Boolean to .Value:
* Drag the DB boolean directly onto the exposed In1.Value pin. The connection is accepted immediately!
Assign Signal Status:
* Set In1.ST to 16#80 (Hexadecimal 80 = Good) in the parameter value column. This ensures the block recognizes the input as valid healthy data.

Comparison of Logic Connection Methods in PCS 7 CFC

The table below compares the three methods for handling multi-input boolean logic in PCS 7 CFC charts.

MethodTarget BlocksEngineering EffortCPU OverheadPreserves APL Quality Status?Expand BIT_LGC InputsElementary AND / ORVery Low (Right-click block)Lowest (Elementary FC call)No (Pure elementary boolean)Convert with StruDiOuLogicDi / And04Moderate (Requires extra block)Minor (Additional FB execution)Yes (Generates full APL struct)CFC Sub-Element Expansion (+)LogicDi / And04Very Low (Direct pin expansion)Low (Direct variable write)Yes (Manual ST assignment)

Verification

To confirm that Data Block connections function properly:
1. In CFC, verify that all interconnected lines appear solid green without dashed conversion errors.
2. Select Chart > Compile > Changes Only. Confirm that compilation completes with zero errors.
3. Switch CFC to Test Mode (Debug > Test Mode).
4. Force or toggle the DB boolean value in a Variable Table (VAT) or online DB monitor.
5. Confirm that the input state on the logic block updates dynamically and the logic gate evaluates the output correctly.

Limitations and Operational Precautions

When using sub-element expansion (In1.Value), never leave In1.ST unconfigured; an unassigned status defaults to 16#00 (Bad), which will cause APL downstream blocks to flag an interlock fault.
Do not mix elementary BIT_LGC gates and APL structured blocks haphazardly; mixing creates scattered quality codes that complicate plant-wide alarm diagnostics.
Avoid expanding elementary AND/OR gates beyond 16 inputs on high-frequency cyclic OBs (like OB38 @ 10ms), as large bitwise evaluations can increase task jitter.
In safety programs (F-CFC), never use standard BIT_LGC or APL blocks; fail-safe logic requires dedicated F-library blocks (F_AND4, F_OR4).

Engineer FAQ

Why does the cursor show a prohibited sign when dragging a DB bit to And04?

CFC enforces strict data type compatibility. The DB tag is an elementary BOOL, whereas And04.In1 is a structured data type requiring both a Value (BOOL) and a ST (BYTE). Dragging an elementary type onto a structured pin triggers a type mismatch error.

What does signal status 16#80 mean in PCS 7?

16#80 represents 'Good' quality according to the IEC 61804 fieldbus standard. It indicates that the process value originates from a healthy, validated source without communication errors or hardware faults.