How to Implement a 10-Minute Maximum Value Peak Tracker in SCL for SIMATIC PCS 7
In SIMATIC PCS 7, calculating the maximum valid measurement of an analog input over a rolling 10-minute period for sliding average calculations is implemented using a custom Structured Control Language (SCL) function block scheduled in a cyclic interrupt organization block (e.g., OB35). The block tracks incoming analog values with valid quality status (ST >= 16#80), stores peak values across discrete sample intervals in an internal buffer, and exposes the peak value upon receipt of a 10-minute timer pulse while resetting the accumulator. This eliminates memory exhaustion and provides deterministic peak tracking without requiring large FIFO arrays.
Table of Contents
- Mathematical and Operational Requirements for Peak Detection
- Algorithmic Architecture: FIFO Array vs Interval Peak Accumulator
- Structured Control Language (SCL) Implementation Code
- SCL Parameter and Interface Definition Reference
- Verification
- Limitations and Operational Precautions
- Engineer FAQ
- Technical References
- Related Articles
- Related Tags
Mathematical and Operational Requirements for Peak Detection
In continuous process automation applications (such as environmental emissions monitoring, peak power demand limiting, or furnace temperature profiling), control engineers frequently need to determine the maximum valid measurement of an analog process variable (AI) over a discrete time window (e.g., 10 minutes) and pass that value into downstream rolling average calculations (e.g., a 6-sample sliding hourly average).
Key operational prerequisites for process compliance:
1. Quality Code Validation: In PCS 7 APL, analog values are structured variables (STRUCT containing Value: REAL and ST: BYTE). The peak calculator must ignore invalid measurements (ST < 16#80 such as bad sensor quality, open wire, or out-of-range faults) so bad values do not distort peak calculations.
2. Deterministic Resetting: Every 10 minutes, the determined maximum value must be frozen and presented at the output, while the internal peak tracker resets to current live measurement for the subsequent 10-minute interval.
Algorithmic Architecture: FIFO Array vs Interval Peak Accumulator
Engineers often consider two programming approaches in S7-400 / CPU 410-5H controllers:
Approach A: Continuous FIFO Ring Buffer
- Stores individual samples (e.g., 1 sample per second = 600 elements in a
REALarray). - Every cycle, shifts the array and iterates through 600 elements using a
WHILEloop to find the maximum. - Drawback: Significant CPU cycle load; a 600-element loop executed every cycle in OB35 introduces unnecessary cycle latency and increases communication jitter.
Approach B: Interval Peak Accumulator with Periodic Staging (Optimal)
- Compares the live valid measurement against a single running maximum variable (
rRunningMax) each cycle. - If
PV_In.Value > rRunningMax, updaterRunningMax := PV_In.Value. - An external or internal 10-minute timer generates a single-cycle pulse (
Trigger_10Min). - On trigger pulse:
- Transfer running maximum to output:
Max_PV_Out := rRunningMax. - Reset running maximum to current measurement:
rRunningMax := PV_In.Value. - Advantage: Execution time is sub-microsecond with zero looping overhead, fitting cleanly into standard cyclic interrupt tasks.
Structured Control Language (SCL) Implementation Code
The following production-ready SCL function block implements interval peak detection with signal quality filtering:
FUNCTION_BLOCK "FB_PeakTracker_10Min"
TITLE = '10-Minute Analog Peak Tracker'
AUTHOR : 'CieloEng'
VERSION : '1.0'
VAR_INPUT
PV_In : STRUCT // Analog Input with APL Quality Code
Value : REAL;
ST : BYTE;
END_STRUCT;
SampleTrigger : BOOL; // Sample Enable Pulse (e.g., 1s pulse)
PeriodTrigger : BOOL; // 10-minute rollover pulse
Reset : BOOL; // Manual Reset Command
END_VAR
VAR_OUTPUT
Max_PV_Out : REAL; // Latched Maximum over last 10 minutes
Current_Peak : REAL; // Active running peak of current window
Valid_Sample : BOOL; // Quality indicator
END_VAR
VAR
rRunningMax : REAL := -3.402823e+38;
bFirstScan : BOOL := TRUE;
bTrigSav : BOOL := FALSE;
bRstSav : BOOL := FALSE;
END_VAR
BEGIN
// Validate Signal Quality (APL Good Quality >= 16#80)
Valid_Sample := (PV_In.ST >= 16#80);
// Initialization on First Scan
IF bFirstScan THEN
IF Valid_Sample THEN
rRunningMax := PV_In.Value;
ELSE
rRunningMax := 0.0;
END_IF;
Max_PV_Out := rRunningMax;
bFirstScan := FALSE;
END_IF;
// Manual Reset Command (Rising Edge)
IF Reset AND NOT bRstSav THEN
IF Valid_Sample THEN
rRunningMax := PV_In.Value;
ELSE
rRunningMax := -3.402823e+38;
END_IF;
END_IF;
bRstSav := Reset;
// Cyclic Evaluation on Valid Sample
IF Valid_Sample THEN
IF PV_In.Value > rRunningMax THEN
rRunningMax := PV_In.Value;
END_IF;
END_IF;
// 10-Minute Rollover Trigger (Rising Edge)
IF PeriodTrigger AND NOT bTrigSav THEN
Max_PV_Out := rRunningMax;
IF Valid_Sample THEN
rRunningMax := PV_In.Value;
ELSE
rRunningMax := -3.402823e+38;
END_IF;
END_IF;
bTrigSav := PeriodTrigger;
// Expose running peak
Current_Peak := rRunningMax;
END_FUNCTION_BLOCK
SCL Parameter and Interface Definition Reference
The following table outlines the interface definitions and attributes for the custom peak tracker block:
PV_InSTRUCT (Value: REAL, ST: BYTE)Pcs7AnIn.PV_OutSampleTriggerBOOLPeriodTriggerBOOLTIMER_P.Q0 (600s pulse)ResetBOOLMax_PV_OutREALCurrent_PeakREALValid_SampleBOOLInterconnecting Max_PV_Out to an APL Smooth or FIFO calculation block generates rolling hourly metrics cleanly.
Verification
To verify block operation in CFC Test Mode:
1. Compile the SCL source file to generate an FB in the offline block folder.
2. Instantiate the block in a CFC chart running in OB35 (100 ms).
3. Connect PV_In to an analog generator and PeriodTrigger to a test timer (e.g., set to 10 seconds for rapid testing).
4. Vary the input value: observe that Current_Peak tracks upward whenever a new higher value occurs, but does not decrease when the input drops.
5. Invert PV_In.ST to 16#00 (Bad Quality); confirm that spikes with bad quality are ignored by Current_Peak.
6. Trigger PeriodTrigger; confirm that Max_PV_Out assumes the peak value and Current_Peak resets to the live input.
Limitations and Operational Precautions
- If all samples within a 10-minute period possess bad quality (
ST < 16#80),Max_PV_Outretains the minimum initialization value; add downstream quality handling to flag the period as invalid. - Never run unbounded
WHILEloops in S7-400 SCL code; if a loop condition fails to terminate, the CPU cycle execution time will exceed the watchdog limit, triggering a STOP via OB80. - Ensure the period trigger pulse is asserted for exactly one CPU cycle to prevent multi-cycle accumulator resetting.
- When compiling SCL in PCS 7, ensure that 'Create Block Icons' and 'Create S7_m_c attributes' are enabled if WinCC monitoring is required.
Engineer FAQ
Why is ST >= 16#80 used to check quality in SCL?
In SIMATIC PCS 7 APL, signal status bytes follow NAMUR NE107 standards where values of 16#80 or higher represent 'Good' or 'Good, maintenance demanded' quality. Values below 16#80 indicate simulated, degraded, or bad values.
How do I generate a deterministic 10-minute pulse in CFC?
Use the standard Basis Library block TIMER_P configured as a pulse generator with a time parameter TI := T#600s, or count execution cycles of OB35 (e.g., 6000 cycles of 100 ms).
Can I compile this block into a CPU 410-5H without re-allocating memory?
Yes, importing and compiling a new function block in SCL creates a new FB number in the offline folder, which can be downloaded changes-only in RUN mode.
Technical References
- SIMATIC S7-SCL for S7-300/400 Programming Manual
- SIMATIC PCS 7 Advanced Process Library Basics Manual
- Siemens Industry Online Support FAQ: Signal Status in PCS 7 APL
Related Articles
- How to Enable the Faceplate Reset Button and Clear Undefined States on APL Valve Blocks in PCS 7
- Understanding Question Mark and Exclamation Mark Block Header Symbols in SIMATIC CFC
- How to Measure and Analyze Network and Communication Bus Load in SIMATIC PCS 7
Related Tags
- SCL_Programming
- Peak_Tracker
- CFC_Logic
- Analog_Processing
- Signal_Status