How to Implement a Retentive Pause-Resume Timer in SIMATIC PCS 7 APL Using TimerP and Custom SCL

In SIMATIC PCS 7 Advanced Process Library (APL) V8.0, standard timer blocks such as TON reset their accumulated elapsed time to zero immediately when the timing condition transitions to false. To implement a retentive timer that pauses and freezes its elapsed time when conditions go false, resumes when conditions return to true, and sets an output flag when elapsed time reaches a preset value, engineers can utilize the APL 'TimerP' block by dynamically manipulating its block enable input 'EN'. Alternatively, a fully encapsulated retentive timer block can be coded in Structured Control Language (SCL) by integrating cyclic sampling time ('SAMPLE_T') when active, holding the accumulated accumulator when paused, and clearing only upon an explicit reset pulse.

Standard Timer Behaviors vs Retentive Pause-Resume Requirements

In process automation applications such as CIP (Clean-in-Place) wash cycles, catalyst exposure tracking, and filter backwashing:
* The Process Requirement: A process timer must accumulate running time only while certain conditions are satisfied (e.g., wash pump running AND temperature above 75 deg C). If temperature dips below 75 deg C, the timer must pause and hold its elapsed time. When temperature recovers, timing must resume from the frozen value.
* The Standard IEC Limitation: Standard IEC timers (TON - SFB4) are non-retentive; setting input IN := FALSE immediately clears the internal elapsed time (ET := T#0ms) and drops output Q.
* The APL Solution: Engineers must either adapt standard APL timing blocks or create custom SCL logic to provide retentive pause/resume functionality.

Implementing Retentive Timing Using APL TimerP and Block Enable (EN)

The TimerP block (FB1810) from the PCS 7 Basis / APL Library can be adapted to achieve pause-resume timing without writing custom code:

Operating Mode Selection:
* Parameter Mode: Set to 0 (Pulse), 1 (Extended Pulse), or 2 (On-Delay) depending on target output behavior.
* Set parameter Ti to the target duration in seconds (e.g., 120.0 s).
Utilizing Block Enable (EN):
* By default in CFC, the block enable input EN is hidden and tied to CPU execution.
* In CFC, right-click the TimerP block: select Object Properties > I/Os.
* Locate parameter EN and uncheck the Invisible attribute.
* Interconnect the process running condition (e.g., Pump_Run AND Temp_OK) directly to EN.
* Interconnect the trigger signal to In.
Execution Behavior:
* When EN = 1, TimerP executes cyclically, advancing elapsed time.
* When EN = 0, the S7 CPU skips execution of the block instance completely; its internal static memory retains the exact millisecond count where it stopped.
* When EN returns to 1, execution resumes seamlessly from the frozen value.

Developing a Dedicated Retentive Timer Block in SCL

While TimerP with EN works, manipulating EN prevents the block from reporting frozen status to WinCC faceplates. Writing a custom SCL block using cyclic sampling time (SAMPLE_T) delivers a cleaner, fully observable solution:

FUNCTION_BLOCK FB_RetentiveTimer
TITLE = 'APL Retentive Accumulation Timer'
VERSION : '1.0'
AUTHOR : 'Cielo'
FAMILY : 'APL_TIM'

VAR_INPUT
    In_Cond     : BOOL;     // Timing condition (TRUE = Run, FALSE = Pause)
    Reset       : BOOL;     // Explicit Reset (Clears accumulator)
    PresetTime  : REAL;     // Target duration in seconds
    SAMPLE_T    : REAL;     // Sampling cycle time in seconds (from PCS 7 OB)
END_VAR

VAR_OUTPUT
    Q           : BOOL;     // Timer Expired output flag
    ElapsedTime : REAL;     // Accumulated elapsed time in seconds
    Remaining   : REAL;     // Remaining time in seconds
END_VAR

BEGIN
    // Explicit reset overrides all operations
    IF Reset THEN
        ElapsedTime := 0.0;
        Q := FALSE;
    ELSIF In_Cond AND NOT Q THEN
        // Accumulate cyclic sampling period
        ElapsedTime := ElapsedTime + SAMPLE_T;
        IF ElapsedTime >= PresetTime THEN
            ElapsedTime := PresetTime;
            Q := TRUE;
        END_IF;
    END_IF;

    // Calculate remaining time
    Remaining := PresetTime - ElapsedTime;
    IF Remaining < 0.0 THEN
        Remaining := 0.0;
    END_IF;
END_FUNCTION_BLOCK

Integrating Retentive Timing in Continuous Function Charts (CFC)

To deploy the custom SCL retentive timer block in PCS 7:

Insert into Cyclic Organization Block:
* Place the block into a standard cyclic interrupt OB (typically OB35, 100 ms execution frequency).
* PCS 7 automatically connects parameter SAMPLE_T to the task cycle time (0.1 s) during CFC compilation.
Interconnecting Signals:
* Connect process preconditions to In_Cond.
* Connect sequence abort, batch termination, or operator reset buttons to Reset.
* Connect PresetTime to an operator setpoint from WinCC.
* Connect output Q to the downstream transition condition or step advance logic.

Comparison of Retentive Timing Methods in SIMATIC PCS 7

The table below compares different approaches for implementing retentive timers in SIMATIC PCS 7.

Implementation ApproachPrecisionWinCC Visibility During PauseCode ComplexityCPU Resource ImpactTimerP with EN ManipulationOB cycle (100 ms)Frozen at last value (No active status)Zero code; CFC onlyMinimalCustom SCL with SAMPLE_TExact OB cycleFull visibility; reports Elapsed & RemainingLow (Simple SCL block)MinimalTotalL (APL Integrator Block)High precisionFull APL faceplate integrationModerate CFC wiringModerateLegacy TONR (FC80 from TI-S7)MillisecondLimited faceplate supportLowDeprecated in modern APLStandard TON with Memory HoldPoorRequires external flip-flops & latchesComplex CFC spaghettiHigh complexity

Verification

To confirm that the retentive timer operates as designed:
1. In the CFC editor, open the chart containing the retentive timer and switch to Test Mode.
2. Set PresetTime to 20.0 seconds and apply In_Cond = TRUE.
3. Observe ElapsedTime counting up: when it reaches 8.0 seconds, set In_Cond = FALSE.
4. Verify that ElapsedTime freezes precisely at 8.0 seconds and output Q remains FALSE.
5. Wait 30 seconds: verify that ElapsedTime does not reset or drift.
6. Set In_Cond = TRUE: confirm timing resumes from 8.0 seconds and reaches 20.0 seconds, immediately setting Q = TRUE.
7. Pulse input Reset = TRUE: confirm that ElapsedTime clears to 0.0 and Q transitions to FALSE.

Limitations and Operational Precautions

When using TimerP with EN manipulation, remember that the block's outputs will not update while EN = 0; any downstream logic querying auxiliary status bits will see frozen states.
Ensure that SAMPLE_T is never left disconnected or set to 0.0; without cycle time integration, accumulator algorithms will fail to advance.
Retentive timers maintain their accumulated elapsed time across CPU warm restarts if variables are declared in retentive instance data blocks; ensure restart handling explicitly resets or preserves timers as dictated by process safety rules.
Always validate final software licensing and system documentation against the applicable Siemens catalog and authorized distributor quotation.

Engineer FAQ

Why does standard IEC timer TON reset when input goes false?

By IEC 61131-3 definition, TON is a non-retentive on-delay timer. De-asserting the enable input signals that the timing condition is no longer valid, requiring a complete timer restart upon the next true transition.

Can I view the custom SCL timer values in WinCC?

Yes. By declaring ElapsedTime and Remaining with the attribute { S7_m_c := 'true'; S7_unit := 's' }, the AS-OS compiler will automatically generate WinCC tags for faceplate display.

What happens if PresetTime is modified while the timer is paused?

In the SCL implementation, modifying PresetTime dynamically recalculates Remaining. If the new PresetTime is less than or equal to current ElapsedTime, output Q will trip immediately upon the next execution cycle.