How to Implement Multi-Step Valve Positioning and Incremental Actuator Profiling in PCS 7

To control an analog control valve or damper in five discrete sequential steps with configurable dwell times in SIMATIC PCS 7, engineers should implement either the Industry Library Multi-Position Valve block (VlvPos / DiverterValve) or an Advanced Process Library (APL) sequencer driving VlvAnL. The standard Polygon (Polyg_P) block is a continuous mathematical interpolator that transfers changes instantaneously and cannot provide step delays without external timing. In the APL framework, the recommended approach is pairing VlvAnL with an SFC step sequence or a custom SCL state machine that commands discrete setpoints (e.g., 20%, 40%, 60%, 80%, 100%) through MV_Ext in conjunction with TimerP or TON dwell timers.

Continuous Ramp vs Discrete Multi-Step Positioning

In process automation, certain mechanical systems and thermodynamic operations prohibit sudden or continuous ramping valve travel:

Thermal Shock Prevention: Heating steam valves must open in distinct increments (e.g., 10% dwell for 5 minutes, 30% dwell for 5 minutes, 60% dwell, then 100%) to allow piping to warm up gradually without condensation hammering.
Pressure Surge Mitigation: Hydraulic bypass valves in high-pressure gas lines open in discrete stages to allow pressure equalisation across downstream orifices.
Multi-Port Diverter Dampers: Dampers or rotary multiport valves physically travel between five discrete mechanical stops (Position 1 through 5).

Executing this stepped profile requires an architecture that asserts a target setpoint, halts until a timer or condition is met, and then advances to the subsequent target position.

Why the Polyg_P Characteristic Block Alone Fails for Stepped Movement

Engineers frequently attempt to use the standard mathematical characteristic curve block Polyg_P (Polygon with 8 interpolation points) to generate multi-step outputs:

The Functional Mismatch: Polyg_P is purely a static piece-wise linear function generator:
Y = f(X)
It maps an input X to an output Y instantaneously based on linear interpolation between predefined coordinate pairs (X1, Y1) through (X8, Y8).
If the input X jumps, the output Y jumps instantly. If X ramps continuously, Y changes continuously.
Polyg_P has no internal time delay, state memory, or dwell timers. Attempting to generate five delayed steps using Polyg_P alone is impossible without an external step generator driving X.

Method 1: Using Industry Library Multi-Position Valve (VlvPos)

For projects equipped with the SIMATIC PCS 7 Industry Library (IL):

Deploy VlvPos: Place the multi-position valve block VlvPos from the Industry Library into the CFC chart.
Configure Predefined Positions: VlvPos natively supports up to 8 discrete operating positions (Pos1 to Pos8) parameterized with exact analog percentages (e.g., Pos1 = 0%, Pos2 = 25%, Pos3 = 50%, Pos4 = 75%, Pos5 = 100%).
Step Transition Logic: Operators or higher-level sequence blocks select the target position index (PosOp or PosAut).
Integrated Transit Times and Alarms: VlvPos monitors traveling times, handles limit switch feedback for intermediate positions, and generates specialized multi-position faceplates on WinCC OS.

Method 2: Engineering an APL Sequencer with VlvAnL and TimerP

When working strictly with the standard Advanced Process Library (APL) without the Industry Library add-on, engineer an SCL state machine or CFC sequencer:

1. Control Block Setup

Place VlvAnL (Analog Control Valve).
Configure MV_Ext (External Manipulated Variable setpoint).
Set ModLiOp = 1 and AutModLi = 1 to enable automated setpoint control from CFC logic.

2. Step Sequencer Logic (SCL or SFC)

Implement a 5-step finite state machine:
* State 0 (Idle/Closed): MV_Ext := 0.0.
* State 1 (Step 1): MV_Ext := 20.0. Start timer T1 (PT := T#60s). When T1.Q = TRUE and position feedback verifies 20%, transition to State 2.
* State 2 (Step 2): MV_Ext := 40.0. Start timer T2 (PT := T#60s). Upon expiry, transition to State 3.
* State 3 (Step 3): MV_Ext := 60.0. Dwell 60 seconds.
* State 4 (Step 4): MV_Ext := 80.0. Dwell 60 seconds.
* State 5 (Step 5): MV_Ext := 100.0. Valve fully open.

If an interlock or stop command occurs at any point, the sequencer resets to State 0 immediately.

Multi-Step Positioning Implementation Comparison Matrix

The following table compares the architectural options for multi-step valve positioning in PCS 7:

Solution ArchitectureRequired LibraryEngineering ComplexityFaceplate IntegrationBest Suited ApplicationsIndustry Library VlvPosPCS 7 Industry LibraryLow (Pre-built block)Native multi-position faceplateMulti-port diverters, discrete mechanical stopsAPL VlvAnL + SCL SequencerStandard APLMedium (Custom logic)Standard APL valve faceplateWarm-up sequences, controlled thermal rampingAPL VlvAnL + SFC ChartStandard APLMedium (Graphical SFC)SFC visualization faceplateBatch recipe phases, timed vessel heatingPolyg_P InterpolatorStandard LibraryUnusable aloneStandard analog faceplateContinuous non-linear sensor curve correction

Selecting the appropriate method balances engineering effort with operational visualization clarity.

Verification

To verify that multi-step valve positioning operates correctly:
1. In CFC test mode, trigger the start command for the 5-step positioning sequencer.
2. Verify that VlvAnL.MV_Ext steps to the first setpoint (20%) and remains steady for the configured dwell time.
3. Observe the step progression across all five stages; confirm that transitions occur only when both the dwell timer expires and position feedback confirms travel.
4. On the WinCC valve faceplate, verify that the manipulated variable bar graph reflects each discrete stage.
5. Simulate an interlock trip during Step 3; confirm that the valve aborts immediately to the safe position (0%).

Limitations and Operational Precautions

Ensure valve actuators are rated for repeated positioning stops; rapid stepping on pneumatic positioners without proper dampening can cause mechanical hunting.
Always configure emergency interlocks (Intlock, Protect) directly on VlvAnL, bypassing the step sequencer during safety shutdowns.
If using the Industry Library, verify that your PCS 7 version supports the installed IL release and that appropriate runtime licenses are present.
Always validate final license quantities, module availability, and MLFBs against the applicable Siemens catalog and authorized distributor quotation.

Engineer FAQ

Can I use the APL Ramp function (RampP) instead of stepped positioning?

RampP produces a continuous, linear analog ramp over time. It cannot produce discrete stair-step outputs with dwell plateaus unless paused and resumed via external logic.

What happens if position feedback fails to reach a step target within the dwell time?

The step sequencer should include a position fault watchdog timer. If feedback does not reach tolerance (e.g., target ± 2%) before the dwell timer expires, the sequencer should hold and generate an operator alert.

Does VlvPos require special hardware limit switches for all 5 positions?

No. VlvPos can operate using continuous analog position feedback (4–20 mA potentiometer or digital positioner) to verify intermediate positions mathematically.