Implementing Conditional Daily Real Value Accumulation and Triggered Summation in CFC

In SIMATIC PCS 7 CFC, performing conditional daily summation of REAL numbers (such as calculating daily utility costs or production totals at 23:59:59) should not be implemented using direct recursive feedback (connecting an adder block's output back to its own input), as this creates an unstable algebraic loop warning. Instead, use the APL TotalL block (FB1906) or combine TimeTrig (FB1802) with CountScl (FB1806) or an analog latch circuit. TimeTrig evaluates system time and generates a single-cycle pulse at 23:59:59, which strobes the adder block or triggers a hold buffer. For continuous flow accumulation, TotalL integrates flow rates natively with built-in periodic reset capabilities.

Executive Summary

Process automation projects frequently require recording and accumulating daily totals—such as daily raw material consumption, electrical energy usage, or production batches—at a specific scheduled timestamp (e.g., daily at 23:59:59). In traditional programming languages (C or SCL), this is written as an if (trigger) { sum = sum + daily_value; } statement. In PCS 7 CFC, recursive data loops without sample-delay memory blocks cause compiler cycle warnings, algebraic race conditions, and non-deterministic behavior. This guide details standard engineering patterns using TimeTrig and APL integration blocks to achieve deterministic daily totalization.

Architecture and Fundamental Mechanics

Recursive accumulation in CFC requires careful synchronization with cyclic interrupt execution:
1. Algebraic Loop Hazards:
If the output of an addition block (Add08 or AddR) is wired directly to its own input, the block calculates its output based on its own immediate result in the same OB cycle. This creates an infinite feedback loop during continuous execution unless gated by an edge-triggered latch.
2. Time Synchronization and Triggering (TimeTrig, FB1802):
TimeTrig reads the CPU master real-time clock. When the configured trigger time matches (e.g., hour = 23, minute = 59, second = 59), it asserts a boolean pulse Out for exactly one OB execution cycle.
3. Safe Accumulation Architectures:
- Architecture A (APL TotalL, FB1906): For continuous process rates (e.g., kg/h or m3/h), TotalL integrates the flow value over time. An external pulse from TimeTrig strobes RstLi to snapshot the day's total to an archive register and reset the integrator for the next 24-hour cycle.
- Architecture B (Sample-and-Hold Buffer with ShldR / CountScl): For discrete daily cost additions, the incoming daily total is added to an accumulator register. An edge trigger clocks an analog latch block (ShldR or custom SCL block with internal state memory), storing the cumulative total deterministically.

Step-by-Step Implementation Procedure

Instantiate the Time-Trigger Block in CFC:
a. Open the target CFC chart assigned to cyclic OB35 (100ms) or OB32 (1s).
b. Insert TimeTrig (FB1802) from the PCS 7 Basis Library or APL.
c. Set TrigMode = 1 (Daily trigger at a fixed time).
d. Set Hour = 23, Minute = 59, and Second = 59.
Configure the Accumulator Logic:
a. For continuous integration, insert TotalL (FB1906).
b. Connect the live rate signal (e.g., flow rate or cost per hour) to In.
c. Connect TimeTrig.Out to an analog hold block (ShldR) clock input to capture TotalL.Out right before reset.
d. Pass TimeTrig.Out through a one-cycle delay (TimerP or edge evaluator) to TotalL.RstLi to reset the integrator for the new day.
Configure Discrete Real Addition (Cost Accumulation):
a. If summing pre-calculated daily totals ($Total_{new} = Total_{prev} + DayVal$), insert an addition block (AddR or Add04).
b. Use an analog sample-and-hold block (such as ShldR or SCL-based latch) between the output of AddR and its recursive input.
c. Wire TimeTrig.Out to the sample enable input En of the hold block, ensuring the accumulated register is updated only once per day at 23:59:59.
Compile and Verify Execution Sequence:
a. In CFC, open Edit -> Runtime Sequence.
b. Ensure TimeTrig executes before the accumulator block, and the hold/snapshot block executes before the reset block in the runtime group.

Verification

In CFC test mode, temporarily configure TimeTrig to trigger every minute (e.g., set Second = 30 with minute trigger mode) to observe operation without waiting 24 hours.
Monitor the accumulator block output: confirm that the value remains strictly constant during normal cycles.
When the trigger second arrives, confirm that the hold block captures the accumulated total and the integrator increments or resets precisely by one transaction.
Verify in the CPU diagnostic buffer that no algebraic loop cycle warnings or cycle time overruns are reported.

Limitations and Operational Precautions

Directly feeding an adder's output back to its input without an intervening edge-triggered latch block will cause the adder to increment on every single cyclic interrupt execution (e.g., every 100 ms), resulting in arithmetic overflow within seconds. Always decouple feedback paths with memory latches.

Engineer FAQ

Why does CFC display a warning when connecting a block output back to its input?

CFC detects a direct algebraic loop. Because there is no memory delay between output and input, the calculation order within the same task execution cannot be resolved deterministically.

Can I use an SCL block instead of multiple CFC blocks?

Yes. A custom SCL function block with an internal STATIC REAL variable and an R_TRIG edge detector provides a compact, deterministic solution for daily real value accumulation.

How does TimeTrig handle daylight saving time transitions?

TimeTrig operates on local CPU time or UTC depending on CPU configuration. For critical production accounting, UTC is recommended to prevent skipped or duplicate 23:59:59 triggers.

What is the difference between TotalL and CountScl?

TotalL is designed for continuous integration of flow rates over time (trapezoidal/rectangular integration), whereas CountScl counts discrete integer or real pulses.

What happens to the accumulated value during CPU warm restart (MRES or power cycle)?

Static variables in standard blocks retain their values if the instance DB is non-volatile. However, if the block initializes on startup (OB100), ensure initialization logic does not overwrite the accumulated total.