C135 PCS 7 (PCS7)
6C
6 Cielo Ciencia y Tecnología
·Publicada en C135 PCS 7 (PCS7)

Implementing Continuous Control Valves Using APL Block VlvPosL in SIMATIC PCS 7

Implementing Continuous Control Valves Using APL Block VlvPosL in SIMATIC PCS 7

To implement a continuous, position-controlled valve using the Advanced Process Library (APL) block VlvPosL (FB1898) in SIMATIC PCS 7, interconnect the analog manipulated variable output MV_Out to an analog output driver (Pcs7AnOu), the analog position readback Rbk to an analog input driver (Pcs7AnIn), and discrete limit feedbacks FbkOpen and FbkClose to discrete input drivers (Pcs7DiIn). For valves equipped with torque monitoring, connect torque fault signals to TorqOpen and TorqClose, and connect optional analog torque signals to TorqAct. Configure Feature.Bit0 for startup behavior and configure MonTiDynamic and MonTiStatic to enforce mechanical travel runtime monitoring.

Table of Contents

Executive Summary

In process industries requiring precision throttling—such as steam header pressure reduction, boiler feedwater control, or chemical dosing—standard discrete valve blocks (VlvL, VlvMotL) and elementary analog blocks (VlvAnL) lack the unified capability to manage continuous modulating positioners equipped with discrete limit switches and torque protection. SIMATIC PCS 7 introduced the VlvPosL (FB1898) block within the Advanced Process Library to combine analog setpoint positioning with discrete open/close limit feedback, torque fault protection, and bumpless manual/automatic tracking. However, because Siemens transitioned from legacy Process Tag Types (PTTs) to Control Module Types (CMTs), no pre-assembled PTT template exists in the standard library. System integrators must manually synthesize analog and digital channel driver connections and configure monitoring parameters to avoid positioning lockups and nuisance travel time alarms.

Architecture and Fundamental Mechanics

The VlvPosL block (FB1898) operates as an integrated technological module combining continuous position control with discrete actuator supervision. The core signal flow coordinates the following interfaces:

  1. Manipulated Variable Processing: The operator or an upstream continuous controller (e.g., PIDConL) provides a target position percentage (0.0 to 100.0%) via MV (internal manual setpoint) or MV_Ext (external automatic setpoint). The block processes rate limits (MV_UpRaLim, MV_DnRaLim) and scale limits (MV_OpScale) before outputting the processed analog signal at MV_Out, which is interconnected directly to the PV_In of a Pcs7AnOu (FB1870) channel driver.

  2. Position Readback (Feedback): The physical actuator stem positioner delivers a 4–20 mA or HART feedback signal routed through a Pcs7AnIn (FB1869) channel driver. The driver's PV_Out connects to the Rbk input of VlvPosL. The block computes the deviation between MV_Out and Rbk. If the deviation exceeds ER_AlmLim for a duration longer than ER_AlmTi, the block asserts a dynamic positioning fault.

  3. Discrete Limit & Torque Supervision: Physical end-stop limit switches wire to digital input cards and route via Pcs7DiIn (FB1865) blocks into FbkOpen and FbkClose. When the valve reaches full travel, end position verification suppresses spurious position alarms. Discrete torque switches wire into TorqOpen and TorqClose. If an obstruction creates excessive stem resistance during opening or closing, the block instantly de-energizes directional travel commands and issues a protective torque trip.

  4. Technological Mode and Interlocks: VlvPosL supports standard APL operating modes (Manual, Automatic, Local, and Out of Service). Safety interlocks (Permit, Protect, Intlock) override manual and automatic positioning commands, driving the valve to its configured safe de-energized or failsafe position via SafePos.

Step-by-Step Implementation Procedure

Execute the following configuration sequence in SIMATIC Manager and the CFC Editor:

  1. Instantiate Drivers and VlvPosL in CFC:
    - Open the target CFC chart in the Plant Hierarchy.
    - From the PCS 7 APL V9.0 catalog, drag VlvPosL (FB1898) into the chart.
    - Place one Pcs7AnOu (FB1870) block for the analog actuator output.
    - Place one Pcs7AnIn (FB1869) block for the position readback signal.
    - Place two Pcs7DiIn (FB1865) blocks for FbkOpen and FbkClose limit switches.
    - If discrete torque switches are present, place two additional Pcs7DiIn blocks for TorqOpen and TorqClose.

  2. Interconnect Channel Drivers:
    - Connect VlvPosL.MV_Out to Pcs7AnOu.PV_In.
    - Connect Pcs7AnIn.PV_Out to VlvPosL.Rbk.
    - Connect limit switch driver outputs Pcs7DiIn_Open.PV_Out to VlvPosL.FbkOpen and Pcs7DiIn_Close.PV_Out to VlvPosL.FbkClose.
    - Connect torque driver outputs Pcs7DiIn_TorqO.PV_Out to VlvPosL.TorqOpen and Pcs7DiIn_TorqC.PV_Out to VlvPosL.TorqClose.

  3. Parameterize Scaling and Operating Ranges:
    - Set VlvPosL.MV_OpScale.High to 100.0 and Low to 0.0 (or engineering units appropriate for the valve travel).
    - Parameterize RbkOpScale to match the physical position transmitter measurement limits.
    - Set MonTiDynamic to the maximum allowable travel time (e.g., 30.0 s) and MonTiStatic to settling tolerance time (e.g., 3.0 s).
    - Configure ER_AlmLim (tracking deviation tolerance, e.g., 2.0%) and ER_AlmTi.

  4. Configure Feature Bits:
    - In the block properties or I/O view, configure Feature.Bit0 = 1 (Startup characteristics: set to defined state on AS restart).
    - Configure Feature.Bit4 = 1 if operator setpoint input should bump the block automatically to Manual mode.
    - Configure Feature.Bit9 = 0 or 1 depending on whether substitution values are desired upon readback driver bad quality.

  5. Compile and Download:
    - Perform a CFC compile with 'Generate module drivers' selected to wire diagnostic and raw hardware address links.
    - Download the changes to the S7-400 AS and compile the WinCC OS to generate faceplates and block icons.

Verification

Verify the implementation through systematic functional commissioning:

  1. Signal Quality Inspection: Open the CFC online and confirm that Pcs7AnIn.PV_Out.ST == 16#80 (Good) and Pcs7AnOu.PV_In.ST == 16#80. Verify that VlvPosL.Rbk.Value matches the field position transmitter value.

  2. Manual Throttling Test: Open the VlvPosL WinCC faceplate. Select Manual mode. Enter setpoints of 25%, 50%, 75%, and 100%. Confirm that MV_Out updates instantly, the field positioner drives the actuator smoothly, and Rbk tracks within ER_AlmLim without triggering tracking alarms.

  3. Limit Switch Alignment: Drive the valve to 0.0% and 100.0%. Confirm that FbkClose and FbkOpen illuminate on the faceplate at the exact calibrated mechanical stroke thresholds.

  4. Torque and Interlock Protection: Simulate a contact closure on TorqOpen while driving the valve open. Confirm that the block immediately halts travel, displays 'Torque Fault Open' on the WinCC alarm banner, and requires an operator reset (RstOp or button).

Limitations and Operational Precautions

VlvPosL requires rigorous configuration of channel driver quality status codes. If Rbk receives bad quality (ST < 16#80), VlvPosL triggers a readback error and, depending on Feature.Bit9, freezes the output or forces the valve to SafePos. Do not connect discrete limit switches directly without Pcs7DiIn drivers, as signal status propagation is mandatory for APL interlock evaluation. Furthermore, note that VlvPosL does not provide an integrated PID algorithm; continuous loop regulation must be executed by an upstream controller block such as PIDConL or PIDConR.

Engineer FAQ

Why is there no default Process Tag Type (PTT) template for VlvPosL in the standard APL library?

Siemens deprecated the creation of new Process Tag Types starting with PCS 7 V8.1/V8.2 in favor of Control Module Types (CMTs). Because VlvPosL was introduced in later APL releases, Siemens expects engineers to implement it as a custom CMT within the Master Data Library rather than maintaining legacy PTT templates.

How does VlvPosL differ from VlvAnL in practical engineering?

VlvAnL is primarily designed for analog control valves without discrete limit switches or torque monitoring, treating end positions purely mathematically based on readback percentage. VlvPosL incorporates dedicated digital limit switches (FbkOpen, FbkClose), torque fault inputs (TorqOpen, TorqClose), and directional control commands.

Can VlvPosL be operated without physical limit switch feedbacks?

Yes. If the valve only provides a 4–20 mA position readback without physical limit switches, set NoFbkOpen = 1 and NoFbkClose = 1. VlvPosL will calculate virtual end positions when Rbk crosses configured threshold limits (e.g., > 98% for open, < 2% for closed).

What causes the valve to trigger nuisance dynamic monitoring faults during movement?

Nuisance monitoring faults occur when MonTiDynamic is set shorter than the physical actuator stroke time, or when ER_AlmLim is set narrower than the hysteresis of the positioner. Ensure MonTiDynamic encompasses full full-stroke transit time plus margin.

How do I link VlvPosL to an upstream PIDConL controller?

Interconnect PIDConL.MV directly to VlvPosL.MV_Ext, and connect VlvPosL.MV_ExtAct back to PIDConL.MV_Trk or use the APL cascade tracking interconnects to ensure bumpless manual-to-automatic transitions when the valve is switched locally.

Technical References

Related Articles

Related Tags

  • VlvPosL
  • APL
  • CFC
  • Channel Drivers
  • Positioner
  • WinCC Faceplate
20 respuestas