Implementing Post-Condition Transition Delays and Step Wait Times in SIMATIC PCS 7 SFC

In SIMATIC PCS 7 Sequential Function Charts (SFC), implementing a dwell time or delay that starts only after process transition conditions are met cannot be achieved using a step's minimum run time, because minimum time begins counting upon step activation. The cleanest and most maintainable engineering approach is to insert an intermediate 'Dwell/Wait' step immediately following the satisfied process condition, configured with a minimum run time and followed by an unconditional transition (TRUE). Alternatively, instantiate a TIMER_P block in CFC.

Execution Mechanics of SFC Steps and Transitions

In SIMATIC PCS 7 sequential control logic, Sequential Function Charts (SFC types and SFC charts) follow the IEC 61131-3 standard. Each phase of an SFC sequence alternates between Steps and Transitions:
* Step Execution: When a step becomes active, the operating system executes its Initialization actions once, then executes its Processing actions every cyclic scan cycle. When the subsequent transition is satisfied, it executes its Termination actions once and deactivates.
* Transition Evaluation: Transitions continuously evaluate Boolean logic equations. When all transition criteria become true, the transition becomes valid and control passes to the next step.

A common automation requirement is to enforce a post-condition delay: the sequence must wait a fixed dwell time (e.g., 30 seconds for chemical mixing or pressure stabilization) only after a physical process threshold is attained (e.g., Temperature >= 80 °C).

Novice engineers often configure the Minimum run time (T_MIN) property on the main step. However, T_MIN starts counting at the exact millisecond the step is entered. If heating the reactor takes 15 minutes, T_MIN (30 seconds) expires long before the temperature threshold is reached, causing the sequence to transition instantly upon reaching 80 °C without any post-condition dwell.

Delay Implementation Methods Comparison Table

Evaluate the three recognized architectural solutions for post-condition delays in PCS 7 SFC:

Implementation MethodEngineering ComplexityResource ConsumptionMaintainability & ReadabilityOperator Visibility in WinCCIntermediate Dwell Step (Recommended)Low (Native SFC structure)Zero additional blocks or licensesHigh; self-documenting in SFC Editor and OS FaceplateHigh; active step name displays 'Dwell' with remaining timeCFC TIMER_P (FB5) / TimP_8Medium (Requires CFC interconnection)Consumes 1 CFC block instanceMedium; logic split between CFC chart and SFC transitionModerate; timer value must be linked to WinCC faceplateCustom SCL Block with Internal TimerHigh (Requires custom block authoring)Consumes user FB/DB and AS POLow; custom code requires maintenance across upgradesModerate; requires custom faceplate elementsSCL Sleep() Call (Prohibited)Invalid (Causes CPU Crash)Overflows cyclic scan timeProhibited; causes OB 80 cycle timeout and CPU stopN/A

Design recommendation: The intermediate step pattern is the industry standard for PCS 7 batch operations and validation compliance.

Implementing the Intermediate Dwell Step Design Pattern

To implement a robust, readable post-condition delay using native SFC constructs:

Structure the Step-Transition Sequence:
* Let Step 1 be the active operational step (e.g., Heat_Reactor).
* Configure Transition 1 (T_Temp_Reached) to monitor the physical condition:
Reactor_Temp.PV_Out >= 80.0
Insert the Intermediate Wait Step:
* Directly below Transition 1, insert a new step named Dwell_Wait.
* Double-click Dwell_Wait to open Step Properties.
* Under the Times tab, set:
- Minimum run time: T#30s (or link to a recipe setpoint variable).
- Maximum run time: T#60s (optional supervision timer).
- Leave Initialization, Processing, and Termination actions empty (or maintain heating control if temperature must be held).
Configure the Subsequent Transition:
* Insert Transition 2 (T_Dwell_Done) immediately below Dwell_Wait.
* In Transition 2 condition logic, enter simply:
TRUE (or 1)
* Because Transition 2 is unconditionally true, the SFC engine evaluates the T_MIN property of Dwell_Wait. The sequencer remains held in Dwell_Wait for exactly 30 seconds after T_Temp_Reached is satisfied, then immediately advances.

Alternative Implementation Using CFC TIMER_P and Feature Bits

If plant guidelines require the delay logic to reside in the CFC layer:
1. Place a standard library timer block TIMER_P (FB5) or APL TimerP in the technological CFC chart.
2. In CFC, configure MODE = 0 (Pulse timer) or MODE = 1 (On-delay timer).
3. Connect the process condition output (e.g., comparator Temp_OK) to the START input of TIMER_P.
4. Set preset time parameter TI to T#30s.
5. In the SFC transition logic, evaluate:
Temp_OK.Out = TRUE AND Timer_Mix.Q = TRUE
6. In the preceding SFC step's Termination actions, pulse RESET on TIMER_P to clear the timer for subsequent cycles.

Verification

Verify delay execution:
1. Open the SFC chart in SFC Editor and switch to Test > Monitor On.
2. Force the process variable below the threshold (e.g., 75 °C): Confirm that Step 1 remains active and Transition 1 is red (not satisfied).
3. Force the process variable above the threshold (e.g., 82 °C): Confirm that Transition 1 turns green and control immediately transfers to Dwell_Wait.
4. Observe the elapsed time counter on Dwell_Wait: Confirm it counts from 0 up to 30 seconds while holding the sequence.
5. Upon reaching 30 seconds, confirm that control seamlessly advances to Step 2.

Limitations and Operational Precautions

Never attempt to program synchronous wait loops (e.g., FOR i := 1 TO 1000000 DO; or Sleep()) inside SCL blocks executed by cyclic organization blocks (OB 30-38). This blocks the CPU execution thread, triggering organization block OB 80 (Cycle Time Exceeded) and halting the automation station.
When configuring recipe-driven minimum times in SFC Types, ensure setpoint limits enforce a positive time value (e.g., T#1s to T#2h) to prevent division-by-zero or negative time overflow exceptions.
In manual operating mode, operators can bypass T_MIN if granted emergency step transition rights (Authorization Level 1100).

Engineer FAQ

Why can't I just use a delay function inside the transition logic itself?

SFC transitions are purely Boolean combinatorial evaluation expressions. They cannot store state or execute timers natively. Time-based transitions must evaluate the running time of the preceding step or an external CFC timer block.

How does the operator monitor remaining dwell time on the WinCC OS faceplate?

When the intermediate step is active, the standard SFC faceplate displays the step name ('Dwell_Wait') and an elapsed/remaining time progress bar derived from the step's minimum run time property.

Can the minimum run time of an SFC step be modified from WinCC Runtime?

Yes. In SFC Types, the step's minimum time can be configured as a runtime setpoint, allowing authorized operators or SIMATIC BATCH recipes to alter dwell times dynamically.