C135 PCS 7 (PCS7)
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Integrating SITOP PSE200U Selectivity Modules with Library V3.4 in PCS 7 V8.2

Integrating SITOP PSE200U Selectivity Modules with Library V3.4 in PCS 7 V8.2

To successfully integrate a SITOP PSE200U selectivity module using the SITOP PCS 7 Block Library V3.4 on a SIMATIC PCS 7 V8.2 system, ensure that the SITOP diagnostic block 'SITOP_Select' is assigned to an active cyclic interrupt OB (e.g., OB35), and that the physical digital input reading the module's single-wire diagnostic output is connected directly to a high-speed discrete input module without hardware input delay filters. If the block fails to decode channel states, verify that the module's diagnostic pulse train is not distorted by software cycle times or digital input RC filtering.

Table of Contents

Executive Summary

SITOP PSE200U selectivity modules divide 24V DC control power into multiple individually monitored 24V feeder circuits, providing electronic overcurrent protection and fast channel tripping. To transmit diagnostic data—such as channel status, load current, and trip causes—back to PCS 7 without requiring expensive fieldbus interfaces, the module utilizes an innovative single-wire serial pulse interface. When deploying SITOP Library V3.4 on PCS 7 V8.2, engineers frequently find that channel faceplates remain uninitialized or fail to decode data. This guide provides the hardware and software configuration steps to establish reliable communication.

Architecture and Fundamental Mechanics

SITOP Single-Wire Serial Diagnostic Protocol and Block Mechanics:

  • The Single-Wire Serial Interface:
  • The SITOP PSE200U (e.g., 4-channel module) provides a single terminal labeled 'Status' or 'Diagnostic Output'.
  • Instead of standard continuous on/off voltage, it transmits a Manchester-encoded serial pulse train containing channel statuses and current levels.
  • Hardware Reading Constraints:
  • The serial pulse width is in the millisecond range.
  • If the S7-400 digital input module (e.g., SM 421) has an input delay filter set to default $3\text{ ms}$ or $15\text{ ms}$, the hardware filter flattens the pulses, causing decoding failure.
  • High-speed inputs with delay set to $\le 0.5\text{ ms}$ or dedicated interrupt inputs are required.
  • The SITOP PCS 7 Library (SITOP_Select):
  • The library provides technological block SITOP_Select and matching WinCC APL-style faceplates.
  • The block decodes the pulse stream, outputting individual channel currents, trip flags, and remote reset triggers.

Step-by-Step Implementation Procedure

Step-by-Step Configuration of SITOP PSE200U in PCS 7 V8.2:

  1. Configure Digital Input Hardware Delay in HW Config:
    - In STEP 7 HW Config, double-click the digital input module connected to the SITOP diagnostic terminal.
    - Open Parameters -> Input Delay.
    - Reduce input delay from default ($3.0\text{ ms}$) to $0.5\text{ ms}$ (or the lowest supported setting).
    - Save and Compile HW Config, then download to the CPU.
  2. Install SITOP Block Library V3.4:
    - Run Setup.exe from the SITOP Library V3.4 installation media on the ES.
    - Open the SITOP Library in SIMATIC Manager; copy block SITOP_Select (and auxiliary blocks) into the Master Data Library.
  3. Place and Wire Block in CFC:
    - Place SITOP_Select into an OB35 chart (cycle time $\le 100\text{ ms}$).
    - Connect the physical digital input address (e.g., I 10.0) to input pin InDiag.
    - Connect a digital output (if remote reset is used) from OutReset to the SITOP reset terminal.
  4. Compile and Update WinCC OS:
    - Compile CFC charts ('Scope: Changes only').
    - In WinCC Explorer, run OS Project Editor to update block typicals.
    - Compile the OS project with 'Create/update block icons' selected.

Verification

To verify SITOP integration:
1. In CFC test mode, observe input InDiag; verify it shows rapid pulse toggling.
2. Observe output Ready and Ch1_Cur, Ch2_Cur; verify they report realistic load currents.
3. In WinCC Runtime, open the SITOP faceplate; verify all 4 channels indicate green healthy status and display live current bar graphs.

Limitations and Operational Precautions

Operational precautions:
- Do not schedule SITOP_Select in a slow cyclic OB (e.g., OB32 - 1000ms); the decoding algorithm requires consistent execution cycles to sample incoming pulse trains accurately.
- Ensure that common 24V ground (M) is securely bonded between the SITOP power supply and the S7-400 I/O subrack to eliminate ground loop voltage offsets.
- Remote reset from the faceplate resets all tripped channels simultaneously; verify that field overloads are resolved before commanding a reset.

Engineer FAQ

How does the SITOP PSE200U transmit diagnostics over a single wire?

It transmits a high-speed serial pulse train containing channel status and load current data over a single discrete terminal.

Why does the SITOP block fail to read data in PCS 7?

Because the physical digital input module has an input filter delay (e.g., 3ms) that smooths out the pulse train. Setting filter delay to 0.5ms resolves this.

What execution cycle is recommended for the SITOP block in CFC?

OB35 with a cycle time of 100ms or faster.

Can I reset a tripped SITOP channel remotely from the faceplate?

Yes, by connecting the block's OutReset output to a digital output wired to the module's reset input terminal.

Does the SITOP library consume an AS Process Object?

Yes, instantiating the technological SITOP_Select block with OCM enabled consumes standard AS/OS Process Objects.

Technical References

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Related Tags

  • SITOP PSE200U
  • Power Supply
  • Selectivity Module
  • Single-Wire Diagnostic
  • SITOP Library
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