Interpreting CFC Feedback Line Indicators and Run Sequence Optimization in PCS 7

In SIMATIC PCS 7 V9.0 and later, a vertical line or plus-like cross symbol displayed on an interconnection line at a block input pin indicates a signal processing feedback loop or inverted runtime sequence. The CFC compiler detects that the target block is scheduled to execute earlier in the CPU runtime group than the block producing the output signal, causing the input to receive data delayed by one execution cycle (OB cycle). To eliminate unexpected processing lag, open the Runtime Editor (or select Options -> Optimize Run Sequence) to reorder block execution according to signal flow. Note that this feedback symbol is distinct from the 'S' indicator, which denotes APL structured connections.

Runtime Execution Order and Signal Flow in PCS 7 CFC

Continuous Function Chart (CFC) is a graphical programming language that compiles into discrete STEP 7 machine code organized into cyclic Organization Blocks (such as OB35, 100ms task). Unlike ladder logic or electrical schematics where power flows strictly from left to right, CFC blocks are placed freely across sheets and chart partitions.

The order in which blocks execute is governed by their position in the CPU runtime tree, not their physical placement on the screen. If Block A generates an analog setpoint that Block B processes, Block A should ideally execute immediately before Block B in the runtime sequence. When execution order aligns with signal flow, data transfers with zero latency within the same OB scan. If Block B executes before Block A, Block B calculates using data from the previous CPU cycle.

Meaning of the Vertical Line Feedback Symbol in CFC V9.0

Starting in SIMATIC PCS 7 V9.0 (CFC V9.0), Siemens introduced dynamic visual feedback markers directly on interconnection lines. When an engineer connects an output pin to an input pin:

Automatic Runtime Evaluation: CFC parses the runtime sequence of both blocks in real time.
Feedback Detection: If the interconnected output originates from a block that executes after the destination block in the runtime group, or if a closed mathematical feedback loop exists (e.g., in anti-reset windup or lead-lag networks), CFC renders a vertical hash line / plus symbol (+) on the interconnection line adjacent to the input pin.
Color Consistency: The indicator adopts the exact color of the interconnection line (e.g., green for REAL, yellow for safety, dark blue for structures), alerting the engineer to the one-cycle processing delay.

Distinguishing Feedback Markers from Structured Connections

Engineers frequently confuse this new runtime indicator with APL data structure indicators:

Structure Symbol ('S'): Appears on block pins and interconnection lines carrying APL structured data types (STRUCT containing Value + ST). It signifies that quality codes and value attributes are packaged together.
Feedback Marker (Vertical Line / Cross): Positioned specifically on the line near the input pin. It denotes temporal execution order (feedback / cycle delay), regardless of whether the signal is a simple BOOL, a REAL, or a complex structure.

Comparison of CFC Connection Visual Indicators

The table below outlines the graphic indicators found on CFC connection lines and pins in SIMATIC PCS 7 V9.0 and later.

Graphic SymbolIndicator NameUnderlying Technical CauseOperational Impact & Recommended ActionVertical Line / Cross (+)Feedback Indicator (Rückkopplung)Target block executes before source block in runtime groupSignal lags by one OB execution scan; optimize runtime sequenceLetter 'S' on Pin/LineStructured ConnectionData type is an APL structure (Value + ST)Normal operation; carries process value and IEEE quality statusDotted Connection LineTextual InterconnectionTarget chart/block not yet compiled or unresolved cross-chart linkNon-functional until charts are compiled or textual link closedInversion Circle / SlashNegated Binary InputBoolean input negated via right-click commandInverts input state (NOT); intentional logic negationYellow Connection LineFailsafe InterconnectionSignal exchanged between F-System safety blocksSafety critical data flow; governed by F-runtime group rules

Step-by-Step Procedure to Optimize Block Runtime Sequence

To resolve inadvertent feedback markers and eliminate one-cycle latency, reorder runtime execution:

Locate the Marked Interconnection:
- In the CFC chart, inspect the input pin displaying the vertical feedback marker.
- Identify the source block providing the output signal.
Open the Runtime Editor:
- In the CFC editor, click the Runtime Editor icon (or press Ctrl + Shift + R).
- Expand the target cyclic task (e.g., OB35 [100ms]).
- Locate the runtime groups containing the source and destination blocks.
Reorder Execution Sequence:
- In the Runtime Editor, click and drag the source block so it appears immediately above the destination block.
- Alternatively, right-click the CFC chart and select Options -> Optimize Run Sequence to allow the compiler to order blocks automatically based on topological signal flow.
Verify Symbol Removal:
- Return to the CFC chart: verify that the vertical line on the interconnection line has disappeared.

Verification

Verify correct signal sequence through the following checks:
1. Check the CFC canvas: confirm that the vertical feedback symbol on the input pin is cleared after optimization.
2. In the Runtime Editor, verify that the source block's execution index is lower than the destination block's index within the same OB.
3. Switch CFC to Online Test Mode: monitor signal propagation and confirm that step-change inputs transfer to downstream blocks without delay.
4. Check compiler log: ensure CFC compilation finishes with zero runtime sequence warnings.

Limitations and Operational Precautions

In true closed-loop feedback algorithms (e.g., feeding an actuator output back into an upstream calculation or anti-windup input), a one-cycle delay is mathematically unavoidable, and the feedback symbol will correctly remain visible. Only optimize run sequences where downstream blocks were unintentionally scheduled before upstream drivers. When using Optimize Run Sequence, review safety-related or sequential charts carefully, as automated reordering can alter execution order across multi-chart systems.

Engineer FAQ

Does the vertical feedback line cause compilation errors?

No. The vertical line is an informational diagnostic indicator, not a fatal compilation error. The chart will compile and download, but the connected input will experience a 1-cycle delay.

Why did this vertical symbol not appear in PCS 7 V8.2?

This graphical feedback detection feature was introduced as part of the CFC V9.0 enhancements to improve algorithmic transparency and assist engineers in identifying execution lag.