Latching and Storing Elapsed Process Duration (REAL) in PCS 7 CFC Using MonAnL or Sample Logic

In SIMATIC PCS 7, where CFC charts execute cyclically, latching and saving an elapsed process time (REAL) from a timer (such as TimerP) at the end of a cycle as 'Last Process Duration' requires sample-and-hold logic. Traditional STEP 7 conditional move instructions are not native to continuous CFC execution. The most robust APL solution is to route the elapsed time to an analog monitoring block (MonAnL FB1845) with its block enable input (EN) exposed. While the process is active, EN is set to 1; when the process completes, the rising edge of the completion flag triggers a reset of EN to 0, freezing block execution and latching the final duration on Out.Value. Alternatively, use an APL Sample block or TotalL to store the frozen floating-point value across subsequent process cycles.

Executive Summary

In batch, dosing, and packaging automation, tracking cycle execution time is critical for equipment benchmarking and process optimization. Engineers transitioning from classic STEP 7 ladder logic (where conditional MOVE or L/T instructions capture values on a single scan) often struggle with PCS 7 CFC's continuous cyclic execution model. An elapsed time counter resets immediately when a new cycle starts, overwriting the previous run's result unless explicitly latched. This guide details multiple proven design patterns in PCS 7 APL—utilizing MonAnL enable gating, APL Sample blocks, and flip-flop storage—to capture, persist, and display the 'Last Process Duration' on WinCC operator screens.

Architecture and Fundamental Mechanics

The cyclic execution paradigm of SIMATIC PCS 7 requires specialized mechanisms to hold floating-point values:
1. CFC Cyclic Execution vs Event-Driven Logic:
- In PCS 7, all blocks in an execution OB (e.g., OB35) execute deterministically every scan cycle (e.g., 100 ms).
- A standard timer (such as TimerP FB1884 or TIME_P) continuously increments its output Time_Out during operation and resets to 0.0 when de-energized.
2. The MonAnL EN Execution Gating Pattern:
- In STEP 7 / CFC, every block possesses an implicit input EN (Enable). By default, EN is invisible and permanently true (1).
- By making EN visible on an analog monitoring block (MonAnL FB1845), the engineer controls block evaluation.
- While EN = 1, MonAnL reads the live elapsed time on PV and passes it to Out.
- When the cycle finishes, EN is transitioned to 0. When EN = 0, the block algorithm ceases execution; the CPU skips the block, and the output Out.Value remains frozen at the exact value calculated during the final active scan.
- MonAnL also provides integrated WinCC faceplate integration, trend archiving, and limit monitoring for cycle durations.
3. The APL Sample Block Pattern:
- The PCS 7 library contains mathematical utility blocks such as Sample or selection multiplexers (Sel01SP).
- A positive edge pulse generated by the process completion signal latches the current timer value into an internal storage variable until the next pulse arrives.

Step-by-Step Implementation Procedure

Instantiate Timer Block in CFC:
a. Open the CFC chart governing the batch or sequence phase.
b. Insert TimerP (FB1884) from the APL Mathematical blocks.
c. Connect the process running signal (e.g., Motor.Run or Step.Active) to In of TimerP.
d. Set Mode to count elapsed time (e.g., pulse or on-delay accumulation in seconds).
Instantiate MonAnL as Duration Storage Block:
a. Insert an instance of MonAnL (FB1845) on the same CFC chart.
b. Name the block Last_Cycle_Duration and assign a descriptive comment (e.g., 'Elapsed Duration of Previous Batch').
c. In block properties, ensure S7_m_c := 'true' to enable WinCC operator visualization.
Expose the Hidden 'EN' Parameter on MonAnL:
a. Select the MonAnL block in the CFC editor.
b. Right-click and select Object Properties -> I/Os.
c. Locate the input parameter EN (Enable).
d. Check the box in the 'Visible' column to make the EN pin appear on the block symbol in CFC.
Configure Gating Logic for EN and PV:
a. Interconnect the elapsed time output (Time_Out or Out) of TimerP to the process value input PV of MonAnL.
b. Create gating logic using an RS flip-flop (FlipFlop / F_RS_FF) or latch:
- When the process starts, the flip-flop sets 1 -> MonAnL.EN = 1 (tracking active).
- When the process completes, a 1-cycle edge pulse resets the flip-flop to 0 -> MonAnL.EN = 0 (freezing Out.Value).
- When a new process begins, the flip-flop sets back to 1, refreshing the duration.
Configure Engineering Units and Faceplate Properties:
a. Set MonAnL.PV_Unit to the appropriate code (e.g., 1001 for seconds, or 1002 for minutes).
b. Compile AS charts and execute an OS compile to generate the WinCC tag and faceplate icon.

Verification

In CFC online, initiate a process run: confirm that TimerP begins counting up and MonAnL.Out.Value tracks the live elapsed time.
Terminate the process: confirm that TimerP resets to 0.0, but MonAnL.Out.Value remains frozen at the final recorded duration.
In WinCC Runtime, open the faceplate for Last_Cycle_Duration: verify the displayed value matches the final elapsed time and persists unchanged until the next process cycle finishes.

Limitations and Operational Precautions

Freezing a block by setting EN to 0 also halts its internal alarm evaluation and message processing. If high duration alarms are required, calculate the alarm comparison before the latch or use an un-gated MonAnL fed by an APL Sample block.

Engineer FAQ

Why can't I use a simple MOVE instruction in PCS 7 CFC?

CFC charts execute continuously every OB cycle; a simple MOVE block updates every scan cycle, requiring additional gating logic to hold values.

What does setting EN to 0 do to an APL block?

Setting EN to 0 disables block execution, causing the block to hold its last computed output values in memory without updating.

Can MonAnL values be logged in WinCC historical archives?

Yes. MonAnL has native WinCC integration (S7_m_c) allowing Out.Value to be logged in WinCC Tag Logging automatically.

What block from the standard library can latch a REAL value on an edge pulse?

The Sample block or a combination of Sel01SP and an edge detection block (R_TRIG) can latch and hold REAL variables.

Does MonAnL retain its frozen value across controller warm restarts?

Yes, if the instance DB is retentive and the EN gating flip-flop maintains its state across restarts.

Technical References

Related Tags

MonAnL
Sample and Hold
TimerP
CFC Logic
Elapsed Time
APL

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Latching and Storing Elapsed Process Duration (REAL) in PCS 7 CFC Using MonAnL or Sample Logic