Latching Transient Trip Signals on PCS 7 Interlock Blocks (FB75 and APL Intlk)

In SIMATIC PCS 7, when fast transient fault signals cause the Standard Library Interlock block (FB75 INTERLOK) to trip a motor or valve without allowing the operator to identify which input caused the trip, the issue stems from the combinational, non-latching nature of FB75. Standard Library FB75 evaluates inputs in real time without internal trip memory. To capture and memorize fast-changing trip signals, engineers must insert an off-delay timer block (such as TIMER_P FB5 in Mode 4) on transient inputs, construct an RS flip-flop latch with operator reset, or modernize the technological logic by migrating to APL interlock blocks (Intlk02, Intlk04, Intlk08) which provide native first-in detection and latched trip memory.

Interlock Processing Architecture: Standard Library vs. APL

In industrial process safety and equipment protection, interlocks ensure that motorized equipment, pumps, and control valves cannot start or remain in operation under unsafe physical conditions (such as high discharge pressure, low lubrication oil level, or emergency stop pushbuttons).

In PCS 7 Standard Library (V6.x / V7.x), interlocking was executed primarily via INTERLOK (FB75). FB75 is a purely combinational boolean logic block providing configurable AND/OR evaluation for up to 10 input channels. Crucially, FB75 maintains zero internal memory: when an input condition drops to 0 (tripping output Q), but bounces back to 1 half a second later, output Q immediately re-asserts to 1. Because the motor block (MOTOR FB66) latches the shutdown command, the motor stops, but by the time the operator opens the faceplate, all interlock inputs show healthy green, leaving maintenance personnel unable to diagnose the root cause.

In contrast, the Advanced Process Library (APL) introduced dedicated interlock blocks (Intlk02, Intlk04, Intlk08) engineered with native first-in detection (FirstIn), individual input latching (Latched), and operator reset commands.

Why Transient Input Trips Clear Without Operator Visibility

The inability of operators to view the cause of tripping in legacy PCS 7 configurations results from three factors:

Disparity Between PLC Cycle Time and HMI Polling: S7-400 cyclic interrupt OBs (e.g., OB35) execute every 100ms. A field pressure switch contact chatter or vibration spike lasting 150ms is captured by the AS logic, tripping the drive. However, WinCC OS communication cycles typically poll tags every 1 to 2 seconds. The transient event begins and clears between polling cycles, making it completely invisible to the SCADA graphic.
Lack of Trip History in Standard FB75: FB75 lacks internal shift registers, edge evaluation flags, or first-in discriminator logic.
Alarm Burst Suppressions: If the transient fault does not persist long enough to satisfy alarm generation thresholds, no entry is logged in the WinCC Alarm Logging archive.

Trip Memory and Latching Implementation Matrix

The following table compares solutions for capturing fast transient interlock signals in PCS 7:

Engineering SolutionCore Block UsedTrip Memory RetentionOperator Reset MechanismImplementation EffortTimer Extension (Off-Delay)TIMER_P (FB5) Mode 4Temporary (e.g., 3 minutes)Automatic expirationLow (1 block per input)CFC RS Flip-Flop LatchRS_FF / Logic gatesIndefinite until manual resetOperator pushbutton / TagMediumFirst-In Logic BlockFIRST_IN / Custom FBIndefinite (flags first cause)Manual reset commandMediumAPL Interlock ModernizationIntlk08 (FB1826)Indefinite (Latched.Value)Integrated APL Reset buttonRecommended DCS standardModule Driver DebouncePcs7DiIn / CH_DIFiltered hardware inputN/A (suppresses false chatter)Low (adjusts filter time)

Step-by-Step Procedure to Implement Trip Latching Logic

To ensure that transient interlock trips are memorized and displayed to plant operators:

Option A: Extend Signal Duration Using TIMER_P (FB5):
- In CFC, locate the fast-chattering input signal entering INTERLOK (FB75).
- Insert a TIMER_P (FB5) block from the standard library between the digital input driver and FB75.
- Configure TIMER_P parameters:
- Set MODE := 4 (Extended pulse / Off-delay mode).
- Set TIME0 := T#180s (holds the trip state for 3 minutes).
- Connect the digital input signal to TIMER_P.I0 and connect TIMER_P.Q0 to INTERLOK.I1.
- When the physical contact trips momentarily, TIMER_P holds the fault state active for 3 minutes, giving the operator ample time to view the tripped input on the faceplate.
Option B: Implement an RS Flip-Flop Trip Latch with Manual Reset:
- Insert an RS_FF block (or set-reset memory logic) in CFC.
- Invert the healthy signal so that a fault generates a positive rising edge to RS_FF.S.
- Interconnect the reset input RS_FF.R to a WinCC operator reset command tag or the motor reset command (RESET).
- Connect the inverted output of RS_FF to the interlock input.
- The interlock remains latched in fault mode until an operator explicitly acknowledges and resets the circuit.
Option C: Modernize to APL Interlock Blocks (Intlk04 / Intlk08):
- Replace FB75 with APL Intlk08 (FB1826).
- In CFC, set parameter Logic := 0 (AND) or 1 (OR).
- To activate latching, set parameter Feature.Bit21 := 1 (Bumpless switchover to automatic mode) and configure latching bits.
- APL interlock faceplates (@PG_Intlk08.pdl) natively display a First-In indicator (red frame) highlighting which of the 8 inputs initiated the trip, holding the indicator until reset.

Verification

Verify trip signal memorization:
1. In CFC online mode, momentarily toggle the interlock input to 0 for one execution cycle, then return it to 1.
2. Confirm that the motor block trips and remains stopped.
3. Open the interlock faceplate or monitor CFC; confirm that the fault indicator remains visually latched.
4. Issue a Reset command from the operator faceplate; confirm that the latched fault clears and the equipment can be restarted.

Limitations and Operational Precautions

TIMER_P Expiration Hazard: In Option A, if the operator arrives after the 3-minute timer expires, the fault memory is lost. Use Option B or C for critical safety equipment.
Hardware Chatter Investigation: If contacts bounce frequently, inspect field limit switches, pressure diaphragms, and terminal tightness rather than merely extending software timers.
Standard Library Obsolescence: Legacy FB75 is functionally superseded by APL interlock blocks; plan library upgrades during major DCS turnarounds.

Engineer FAQ

Why doesn't FB75 INTERLOK save the tripped state?

FB75 is a purely combinational logic block without internal memory registers. Its output immediately reflects current input states.

What does TIMER_P Mode 4 do in PCS 7?

Mode 4 operates as an off-delay timer / extended pulse, maintaining the active state for a specified duration after the triggering input returns to normal.

How does APL handle first-in interlock detection?

APL interlock blocks (Intlk02/04/08) compare input transitions on each CPU cycle, latching the first input that changes to the tripped state and displaying a FirstIn marker on the faceplate.

Can I reset latched interlocks from WinCC?

Yes. In APL, operators click the 'Reset' button on the interlock or drive faceplate. In custom logic, a binary WinCC tag is connected to the latch reset pin.