Latching Tripped Interlock Inputs and Bitmask Value Extraction in PCS 7 APL (Intlk04, Intlk08, Intlk16)

In SIMATIC PCS 7 Advanced Process Library (APL), interlock blocks (Intlk02, Intlk04, Intlk08, Intlk16) evaluate multiple input conditions and can latch tripped states using Feature.Bit0 (interlock with latching / reset required). When inputs trip (e.g., input 1 and input 4 becoming active/tripped), the block evaluates individual bit positions. While the primary interlocking output Out is a boolean, the block internally encodes the state of all inputs into double-word status outputs (such as Status1). If an application requires a numerical bitmask representing active tripped inputs (such as 2^0 + 2^3 = 9), engineers can extract the inverted input states using a standard bit-gathering block (BitsToDw) or evaluate the Status1 word directly in CFC.

Executive Summary

Process safety interlocking often requires capturing and preserving the root cause of an equipment trip, even if the initiating physical transmitter clears immediately (e.g., a momentary pressure spike). Automation engineers frequently ask how to latch tripped interlock inputs in APL and whether the block outputs an integer bitmask (such as $2^0 + 2^3 = 9$ when inputs 1 and 4 are faulted). In the PCS 7 Advanced Process Library, interlock blocks provide native latching mechanisms via Feature.Bit0 and encode channel states into status words. This guide explains how to enable latching, interpret status bitmasks, and construct custom bitmask outputs in CFC.

Architecture and Fundamental Mechanics

The APL interlock family (Intlk02, Intlk04, Intlk08, Intlk16 - FB1824..FB1827) operates via configurable Boolean logic and status reporting:
1. Input Evaluation and Inversion:
Each input In01 through In16 accepts a boolean signal with signal status (ST). The parameter InvIn01..16 configures whether the input is active-high or active-low (fail-safe normally closed vs normally open).
2. Latching Mechanics (Feature.Bit0):
- If Feature.Bit0 = 0 (Non-latched / standard): The output Out reflects live input logic. If an input trips and restores, Out restores automatically.
- If Feature.Bit0 = 1 (Latched interlock): When any input condition trips Out = 0, the block latches the tripped state. Even if the physical input returns to healthy 1, Out remains 0 until an operator or program pulses the RstOp or RstLi reset input.
3. Mathematical Bitmask Encoding:
The block evaluates each channel $k$ ($k = 0..15$). The bitmask value of faulted inputs is calculated as:
$$Bitmask = \sum_{k=0}^{n-1} (\neg In_{k+1}) \cdot 2^k$$
If In01 and In04 trip ($In01 = 0, In04 = 0$), their fault bits are $2^0 = 1$ and $2^3 = 8$, yielding a combined integer bitmask of $1 + 8 = 9$.
4. Status Word Architecture (Status1):
The block continuously writes the active input states, inverted states, and bypassed channels into internal double-word output Status1. In WinCC faceplates, these bits drive the visual dynamic checkmarks and alarm icons.

Step-by-Step Implementation Procedure

Configure the APL Interlock Block in CFC:
a. Open the CFC chart and instantiate an interlock block (e.g., Intlk08, FB1826).
b. Connect process monitoring signals (MonAnL.Trip, MonDiL.Out) to inputs In01 through In08.
c. Configure logic mode: set Logic = 0 for AND logic (all inputs must be 1 for healthy output) or Logic = 1 for OR logic.
Enable Latching Behavior (Feature Bit 0):
a. Open block properties for Intlk08.
b. Inspect parameter Feature.
c. Set Feature.Bit0 = 1 ('Interlock with latching / reset').
d. When any input drops to 0, Out drops to 0 and latches until reset.
Extracting Numerical Bitmask Value in CFC (Method A - BitsToDw):
a. If your application logic or PLC-to-PLC communication requires an explicit numerical integer/dword representing the faulted inputs ($2^0 + 2^3$):
b. Insert inverters (Not08 or individual NOT gates) on inputs In01 through In08.
c. Insert block BitsToDw (FB1817) or BitToDword from the PCS 7 Basis Library.
d. Connect inverted In01 to bit 0, inverted In02 to bit 1, inverted In03 to bit 2, and inverted In04 to bit 3.
e. The double-word output Out of BitsToDw will output exactly integer 9 when inputs 1 and 4 are faulted.
Extracting Bitmask from Status1 (Method B - Advanced):
a. Read output parameter Status1.
b. In CFC or SCL, apply a bitwise AND mask against bits 16 through 23 to isolate the live input fault states directly from the block's internal registers.
Connect Reset Logic:
a. Connect operator faceplate command RstOp or programmatic reset RstLi (from an SFC step or master reset push-button) to clear the latched state once field inputs return to healthy status.

Verification

In CFC test mode, set all inputs In01..In08 = 1: verify Out = 1 and Bitmask = 0.
Simulate a trip on In01 and In04 (In01 = 0, In04 = 0):
- Verify Out transitions to 0.
- Verify the bitmask output calculates $1 + 8 = 9$.
Restore In01 = 1 and In04 = 1:
- Because Feature.Bit0 = 1, verify that Out remains latched at 0.
Pulse input RstLi = 1: confirm that Out resets to 1 and the interlock clears.

Limitations and Operational Precautions

Ensure that safety-critical interlocking relying on latching logic has an authorized, secure reset workflow; clearing latches remotely without verifying field conditions can lead to hazardous restarts.

Engineer FAQ

Which Feature bit enables memory latching on APL interlock blocks?

Feature.Bit0 ('Interlock with latching / reset'). Setting Feature.Bit0 = 1 requires an explicit reset to clear the interlock.

How is the bitmask value 9 calculated for inputs 1 and 4?

Input 1 corresponds to bit 0 ($2^0 = 1$) and Input 4 corresponds to bit 3 ($2^3 = 8$). The sum of active faulted bits is $1 + 8 = 9$.

Does Intlk08 provide an integer bitmask output natively?

The block encodes input states inside its Status1 double-word output. For a dedicated user integer tag, connect inverted inputs to a BitsToDw block.