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Managing Shared Valves Between Multiple SFCs in SIMATIC PCS 7: ShrdResL vs ISA-88 Control Strategies

Managing Shared Valves Between Multiple SFCs in SIMATIC PCS 7: ShrdResL vs ISA-88 Control Strategies

In SIMATIC PCS 7, a single valve Control Module (CM) cannot have block contacts assigned to two different SFC Types simultaneously because PCS 7 enforces exclusive technological ownership. To control a shared valve across verification testing and production routines, engineers have two standard architectures. For free-form SFC charts, insert the APL ShrdResL (Shared Resource Large) coordination block to arbitrate commands, manage command reservation, and prioritize abort states. For modular ISA-88 architectures using SFC Types, implement multiple Control Strategies (e.g., 'Verification' and 'Production') within a single Equipment Module (EM), ensuring strict single-owner arbitration without interconnection conflicts.

Table of Contents

Technological Ownership and Block Contact Constraints in PCS 7

In SIMATIC PCS 7 engineering, the relationship between sequential control logic and physical actuators follows strict technological hierarchy principles. When using SFC Types (Sequential Function Chart Types), block contacts are configured in the Master Data Library to link phase actions directly to Control Module (CM) parameters (such as VlvL.OpenAut or VlvL.CloseAut). A fundamental design constraint of the PCS 7 SFC Type compiler is that a block contact on a specific Control Module instance can only be bound to a single SFC Type. The compiler rejects multi-point SFC Type block contact assignments to prevent conflicting write operations and indeterminate actuator positioning.

In brownfield and greenfield automated plants alike, process engineers frequently require specialized sequences—such as a pre-startup valve seat integrity stroke test, CIP flushing routine, or routine maintenance verification—to exercise the exact same physical valves that later execute standard production recipes. Attempting to create a dedicated 'Verification SFC Type' alongside a 'Production SFC Type' that write to the same valve instance creates illegal duplicate block contact mappings. Resolving this engineering requirement demands selecting between signal arbitration blocks (ShrdResL) or ISA-88 control strategy subdivision within the parent Equipment Module.

Architecture 1: Arbitrating Shared Devices with ShrdResL in SFC Charts

When process sequences are implemented using standard standalone CFC SFC charts (rather than library SFC Types), the recommended Siemens APL pattern employs the ShrdResL (Shared Resource Large) block. The ShrdResL block functions as an intelligent multiplexer and priority arbiter positioned in the CFC chart between multiple calling SFC charts and the target Control Module (e.g., VlvL or MotL).

Key operational mechanisms of ShrdResL include:
- Resource Reservation: An SFC requests control of the shared resource by pulsing Alloc1 through Alloc4. ShrdResL evaluates whether the resource is currently free or possessed by a higher-priority task.
- Command Multiplexing: Once ownership is granted to Channel 1 (e.g., Verification SFC), commands InAut1 are transferred directly to the output OutAut, which interconnects to VlvL.OpenAut.
- Safety & Abort Priority: If an SFC enters an ABORT or HOLD state, ShrdResL handles the release sequence gracefully. Reset and manual/auto handshake signals (RstAut, AutAct) ensure that unexpected sequence terminations return the physical valve to its defined safe state before releasing the reservation token.
- Cascaded Multiplexing: For systems with more than four requesting sequences, multiple ShrdResL blocks can be cascaded hierarchically.

Architecture 2: Implementing Multiple Control Strategies in ISA-88 SFC Types

In modern modular PCS 7 facilities aligned with ANSI/ISA-88 standards and SIMATIC BATCH, equipment control follows an Equipment Phase / Equipment Module (EM) hierarchy. Under ISA-88, an Equipment Module possesses exclusive, perpetual technological ownership of its subordinate Control Modules. Rather than creating two competing SFCs, the correct design pattern integrates multiple Control Strategies (CS) inside a single SFC Type.

Implementation details for multi-strategy SFC Types:
1. Strategy Definition: In the SFC Type characteristics dialog, define Control Strategy 1 as Verification (or Stroke_Test) and Control Strategy 2 as Production (or Dosing).
2. Conditional Step Actions: Within the sequencer topology, branching or step enable conditions evaluate the active strategy parameter (QCS == 1 vs QCS == 2). In the Verification branch, the sequencer cycles VlvL.OpenAut and verifies feedback within limit timers.
3. Clean Phase Lifecycle: When the Verification routine finishes, the sequencer drives the SFC Type to the COMPLETED state, returning the block to IDLE. The production system or supervisory batch recipe can then start the SFC Type under QCS == 2 without any physical or logical resource contention.
4. Coordinator SFC Pattern: If a global pre-startup check requires stroking hundreds of valves simultaneously across multiple technological units, an overarching coordinator SFC triggers START with CS = 1 across all technological unit SFC instances in parallel and monitors their completion flags before authorizing plant startup.

Comparative Matrix: ShrdResL Arbitration vs Multi-Control Strategy Architecture

Selecting the optimal valve sharing method depends on whether the project relies on SIMATIC BATCH, CMT/EMT templates, or standalone SFC charts:

Engineering DimensionArchitecture 1: ShrdResL Block ArbitrationArchitecture 2: ISA-88 Control Strategies (SFC Type)Target Sequencer TypeStandalone SFC Charts (CFC instances)Library SFC Types (Equipment Modules)ISA-88 AlignmentNon-standard; multiplexes shared physical actuatorsStrict compliance; single technological ownerSIMATIC BATCH CompatibilityLimited; requires custom allocation handshakesFully integrated; BATCH selects recipe phases and strategiesCFC Engineering OverheadHigh; requires wiring ShrdResL pins to every shared valveLow; internal sequencer branching inside the SFC TypeActuator Conflict RiskMitigated by priority queuing in ShrdResLCompletely eliminated by mutual exclusion of strategiesExecution SpeedMulti-block scan delays across OB35 execution cyclesInstantaneous state transitions within single SFC Type instanceMaintenance ComplexityHigher; signal tracing across multiple chartsLower; centralized sequencer logic in Master Data Library

Step-by-Step Implementation Workflow for Valve Verification Routines

To implement the recommended ISA-88 Control Strategy approach for valve verification:

  1. Open Master Data Library: Navigate to the SFC Types folder and double-click the target Equipment Module SFC Type.
  2. Configure Control Strategies: Under Characteristics -> Control Strategies, insert two rows: ID 1 (Verification) and ID 2 (Normal_Operation).
  3. Configure Block Contacts: Verify that the valve CM contact (VlvL) is mapped to the internal block contact structure.
  4. Build Sequencer Topologies: In the SFC Type sequencer editor, add an alternative branch immediately following the RUN step evaluated on TARGET_CS == 1 vs TARGET_CS == 2.
  5. Program Verification Sequence: In the Verification branch, configure steps to energize OpenAut = 1, verify limit switch feedback FbkOpenOut = 1, dwell for test duration, de-energize OpenAut = 0, and verify FbkCloseOut = 1. If feedback fails within transit time, trip the step error flag.
  6. Program Sequencer Termination: Ensure both branches terminate into the COMPLETING -> COMPLETED state transitions, cleanly de-asserting all automatic command inputs and leaving the valve in safe de-energized rest state.
  7. Update Block Types: In SIMATIC Manager, execute Options -> Charts -> Update Block Types across all target AS projects to synchronize instances, followed by a delta compile and download.

Verification

Validate the implementation in CFC and WinCC Runtime using the following procedure:

  1. Open CFC test mode and monitor the valve Control Module VlvL.
  2. When triggering the Verification routine, verify that VlvL.AutAct is asserted and the valve transitions from closed to open smoothly.
  3. Verify that VlvL.FbkOpenOut feedback matches physical or simulated travel within the configured MonTiDynamic monitoring time.
  4. Verify that attempting to trigger a conflicting sequence while Verification is active results in an allocation hold or rejection, with no jitter or simultaneous high commands on OpenAut and CloseAut.
  5. Confirm that aborting the verification sequence immediately triggers the safe state logic, driving the valve to its de-energized rest position.

Limitations and Operational Precautions

Ensure adherence to the following design safeguards:

  • Never Interconnect Two Automatic Outputs Directly: Never wire output pins from two different blocks directly to VlvL.OpenAut using OR gates without interlocking logic; if one block resets while the other demands opening, indeterminate cycling occurs.
  • Fail-Safe Valve Isolation: In safety-related processes (Safety Matrix / F-Systems), shared valve logic must never bypass safety shutdown interlocks (Intlock, Protect). Safety interlocks always override ShrdResL and SFC Type commands.
  • SFC Type Instance Memory: Modifying SFC Type characteristics requires updating block types across all AS programs. Verify CPU work memory reserves prior to full compilation.

Engineer FAQ

Why can't I simply use an OR block to combine OpenAut commands from two SFC charts?

Combining commands with a simple OR logic block creates dangerous race conditions. If one SFC enters an abort routine requiring an immediate close while the other demands opening, the valve cannot close safely. Furthermore, OR gates lack reservation tokens, causing potential simultaneous open and close pulsing. ShrdResL provides safe allocation tokens and coordinated resets.

Can an SFC Type dynamically switch between Control Strategies while running?

No. In standard PCS 7 SFC Type execution, a Control Strategy is selected prior to starting or during a hold/restart transition. Once the sequencer is in RUNNING, the active strategy (QCS) cannot be changed mid-stride unless explicitly designed via a state transition path back to HOLDING or COMPLETING.

How many requesting sequences can the ShrdResL block arbitrate?

A single ShrdResL block supports up to four independent requesting channels (Alloc1 to Alloc4). If plant topology requires five or more sequences to share an individual physical asset, you can cascade two ShrdResL blocks hierarchically.

Technical References

Related Articles

Related Tags

  • PCS 7 SFC Types
  • APL ShrdResL
  • ISA-88 Architecture
  • Equipment Module (EM)
  • Control Module (CM)
  • VlvL Valve Control
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