Optimizing Block Execution Order and Runtime Sequences in SIMATIC PCS 7 CFC

Optimizing Block Execution Order and Runtime Sequences in SIMATIC PCS 7 CFC

In modern SIMATIC PCS 7 versions (V7.x, V8.x, and V9.x), the Continuous Function Chart (CFC) editor automatically manages insertion pointers and execution order based on signal flow, rendering the legacy manual 'Define Predecessor for Insertion' procedure largely obsolete for routine engineering. However, manual runtime group optimization remains essential to prevent one-cycle latency (OB execution delays) between field channel drivers (such as Pcs7AnIn), interlocking logic, and technological actuator blocks (such as VlvL or MotL). Engineers can inspect and optimize task allocation by opening the CFC Runtime Editor (Options > Customize > Runtime Groups) to ensure inputs execute prior to control algorithms.

Table of Contents

Executive Summary

In SIMATIC PCS 7, the Continuous Function Chart (CFC) editor serves as the primary graphical programming environment for process control logic. Early versions of STEP 7 and CFC required engineers to manually define a 'Predecessor for Installation' in the runtime group editor before placing new function blocks, ensuring blocks executed in the proper chronological order. While modern PCS 7 releases feature automated insertion pointers that infer execution sequences from graphical placement and signal connections, automated placement can still introduce subtle one-cycle computational delays if input drivers execute after control blocks. Understanding how the CFC runtime editor organizes Organization Blocks (OBs), runtime groups, and execution orders is critical for high-performance process automation. This guide details the historical evolution and current best practices for runtime sequence management.

CFC Runtime Architecture: OBs, Runtime Groups, and Insertion Pointers

The S7-400 CPU executes code cyclically within Organization Blocks (OBs). In PCS 7, technological logic is assigned to cyclic interrupt OBs (such as OB35 / 100 ms, OB34 / 200 ms, or OB32 / 1000 ms). Within each OB, execution is subdivided into Runtime Groups:

  • A Runtime Group is a named container holding a collection of block calls executed sequentially.
  • Each CFC chart automatically generates its own runtime groups upon creation.
  • The Insertion Pointer specifies the exact location within an OB or runtime group where newly placed blocks will be installed.

Evolution of the Insertion Pointer: Manual vs Automated Order

In legacy CFC versions, failing to declare a predecessor meant newly placed blocks were appended to the end of the OB, often placing them outside the intended runtime group.

In modern PCS 7, the editor implements intelligent auto-positioning:

  • When a block is dropped onto a chart, it is automatically assigned to that chart's designated runtime group.
  • When interconnections are drawn, CFC analyzes the directed acyclic graph (DAG) of signal flows and offers the option to Optimize Runtime Sequence during program compilation, reordering blocks automatically.

Preventing One-Cycle Execution Delay in Signal Processing

Despite automated sequence tools, complex feedback loops and cross-chart interconnections can result in an actuator block executing before the input channel driver that provides its process measurement. When this happens:

  1. The actuator block computes its control algorithm using the previous cycle's field data.
  2. The channel driver executes later in the same OB cycle, updating the value for the next cycle.
    This introduces an unnecessary 100 ms transport latency (in OB35), degrading control performance in fast pressure, flow, or compressor anti-surge loops.

Runtime Task Organization and Execution Sequence Matrix

The following table compares the optimal execution sequence of blocks within a standard PCS 7 cyclic interrupt OB:

Execution OrderBlock CategoryRepresentative Block TypesFunctional Objective in CycleDelay Impact if MisorderedStage 1 (First)Hardware Diagnostic DriversOB_DIAG1, RACK, MOD_D1Evaluates hardware status words and bus health.Degraded signal quality delayed by 1 cycle.Stage 2Channel Input DriversPcs7DiIn, Pcs7AnIn, FbAnInReads peripheral I/O and computes engineering units.Process inputs delayed; control loop lag.Stage 3Signal Conditioning / MathFilter, TotalL, AverageSmooths noise and calculates derived process values.Secondary calculation lag.Stage 4Interlock & Permissive LogicIntlk02, Intlk08, LogicEvaluates safety permissive and trip conditions.Interlock trip delayed by 1 cycle.Stage 5Technological ActuatorsPIDConL, MotL, VlvLComputes manipulated variable (MV) or valve commands.Core algorithm execution.Stage 6 (Last)Channel Output DriversPcs7DiOu, Pcs7AnOu, FbAnOuWrites computed commands to physical I/O cards.Immediate physical output update.

Step-by-Step Runtime Sequence Optimization Procedure

Method 1: Using the Automated Runtime Sequence Optimizer in CFC

  1. Open any CFC chart in SIMATIC Manager.
  2. Navigate to Options > Optimize Run Sequence from the menu bar.
  3. Select the target cyclic interrupt OB (e.g. OB35) or choose All OBs.
  4. Click OK. The CFC editor parses all block interconnections and restructures runtime groups to eliminate inverted signal paths.
  5. Review the optimization summary log to confirm that no cyclic recursion deadlocks exist.

Method 2: Manually Inspecting and Adjusting Block Predecessors

  1. In the CFC editor, click the Runtime Sequence button on the toolbar (or press Ctrl+Shift+R).
  2. Expand the target OB (e.g., OB35 [100ms]).
  3. Locate the runtime groups for the specific technological unit.
  4. Verify that channel driver blocks (Pcs7AnIn) are positioned higher in the list than downstream controllers (PIDConL).
  5. To reorder a block, click and drag the block to the desired predecessor position, or right-click a block and select Predecessor for Installation before pasting new blocks.

Verification

To verify that execution sequences are optimized without dead times:

  1. Compilation Check: Compile CFC charts via Chart > Compile > Charts as Program. Ensure that the compiler generates 0 errors and no 'Cycle delay' warnings.
  2. Step-Response Timing Test: In S7-PLCSIM or online AS test mode, inject a step change into the analog input driver. Monitor the technological controller output; confirm that the output updates within the exact same OB cycle.
  3. CPU Execution Time Diagnostic: Open PLC > Module Information > Performance Data. Verify that OB35 execution time remains well within the 100 ms limit (typically <40 ms).

Limitations and Operational Precautions

  • Closed-Loop Recursion Deadlocks: In closed-loop feedback systems (such as PID control where output MV influences process PV), at least one signal path will inevitably exhibit a one-cycle delay. The optimizer prioritizes forward feed paths over feedback lines.
  • Cross-OB Interconnections: Connecting a block in OB35 (100 ms) to a block in OB32 (1000 ms) creates variable execution latencies. Minimize cross-OB interconnections to maintain deterministic cycle timing.
  • Online Delta Download Risk: Reordering large numbers of runtime groups can cause the CFC compiler to declare that an online delta download is impossible, requiring a CPU STOP to download.

Engineer FAQ

Is it necessary to define predecessors manually when creating new CFC charts today?

No. The modern CFC editor automatically assigns newly created charts to sensible default positions in the cyclic interrupt OB and manages internal block sequence.

What happens if an analog output driver executes before the PID controller?

The output card receives the computed control value on the subsequent OB cycle, adding an artificial 100 ms delay to the physical valve actuation.

Can a runtime group be disabled dynamically during CPU RUN mode?

Yes. Each runtime group possesses an 'Active' enable attribute that can be switched on or off via logic, disabling execution of all enclosed blocks.

Technical References

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