Resolving Cyclic Communication Errors and Status Flickering in APL Rcv_AnaVal Blocks

Cyclic communication errors and status flickering (oscillating between 16#80 and 16#00 with RcvMonErr pulsing 0 -> 1 -> 0) on APL Rcv_AnaVal blocks occur when the receive monitoring cycle timeout (RcvMonCy) expires before the sending partner dispatches an update. Unlike binary signals, analog transfer blocks (Snd_AnaVal FB1901) only transmit data upon value changes or when the maximum cycle interval (CylMax) elapses. If the partner controller has steady signals and RcvMonCy is configured less than or equal to CylMax, Rcv_AnaVal times out cyclically. To eliminate the error, configure CylMin = 1, CylMax = 2 on Snd_AnaVal, and set RcvMonCy >= 3 on Rcv_AnaVal, executing both blocks in identical cyclic interrupt OBs.

Underlying Mechanism: APL Inter-AS BSEND and BRCV Execution

Inter-controller communication in SIMATIC PCS 7 between S7-400 or CPU 410-5H stations frequently deploys the APL cross-communication blocks: Snd_AnaVal (FB1901) paired with Rcv_AnaVal (FB1902) for analog values, and Snd_DigVal (FB1903) paired with Rcv_DigVal (FB1904) for discrete states. Under the hood, these blocks utilize system communication functions SFB12 (BSEND) and SFB13 (BRCV) over configured S7 fault-tolerant or ISO-on-TCP connections.

To optimize network bandwidth on the Industrial Ethernet plant bus, Snd_AnaVal does not transmit on every execution cycle. Instead, it implements delta-event transmission: if the input value changes beyond an internal deadband, it transmits immediately. If the process value remains static, Snd_AnaVal holds transmission until a heartbeat interval timer (CylMax) expires.

Root Cause Analysis - CylMax vs RcvMonCy Timeout Mismatch

When process values are calm, Snd_AnaVal relies entirely on parameter CylMax (the maximum number of execution cycles allowed between transmissions). On the receiving station, Rcv_AnaVal monitors the connection using parameter RcvMonCy (the number of cycles allowed before flagging a communication timeout).

If an engineer configures RcvMonCy to a value less than or equal to CylMax (for instance, default settings or mismatched OB scan times), Rcv_AnaVal triggers a watchdog timeout before the sending partner's heartbeat telegram arrives. This results in the observed failure pattern: the block receives a valid telegram (Quality = 16#80), waits for the next telegram, times out after 1-2 seconds (Quality = 16#00, RcvMonErr = 1), and then recovers immediately upon the arrival of the delayed heartbeat telegram.

Parameter Configuration and Execution Timing Matrix

The table below details the critical timing parameters, recommended ratios, and functions for APL analog inter-AS blocks:

Block / ParameterData TypeDefault ValueRecommended ValueEngineering Role & RelationshipSnd_AnaVal.CylMinINT01Minimum execution cycles between consecutive sends (throttles burst traffic).Snd_AnaVal.CylMaxINT102Maximum execution cycles between sends when value is static (heartbeat rate).Rcv_AnaVal.RcvMonCyINT33 to 4Monitoring watchdog cycles. Must satisfy: RcvMonCy > CylMax.Execution OBSystem OBVariableOB33 (500 ms)Both sender and receiver blocks must be called in identical OB cycles.Rcv_AnaVal.RcvMonErrBOOLOutputDynamicAsserts 1 when no telegram arrives within RcvMonCy * OB_Cycle.Rcv_AnaVal.Out.STBYTEOutput16#80Signal status byte: 16#80 = Good, 16#00 = Bad (communication fail).

Step-by-Step Parameter Harmonization Procedure

Align Organization Block Assignment: In CFC on both CPU stations, verify that Snd_AnaVal and Rcv_AnaVal are inserted into cyclic interrupt OBs with identical cycle times (e.g., both placed in OB33 with a 500 ms execution interval).
Configure Sending Block (Snd_AnaVal):
- Set parameter CylMin = 1 (guarantees at least one cycle separation between burst transmissions).
- Set parameter CylMax = 2 (forces a telegram transmission at least every 2 cycles, i.e., $2 \times 500\text{ ms} = 1.0\text{ s}$).
Configure Receiving Block (Rcv_AnaVal):
- Set parameter RcvMonCy = 3 (or 4). At 500 ms OB cycles, a setting of 3 establishes a $1.5\text{ s}$ timeout window, providing a $500\text{ ms}$ buffer above the $1.0\text{ s}$ transmission rate.
Verify R_ID Consistency: Confirm that the communication identification parameter R_ID is identical on both paired blocks and unique across the entire S7 connection.
Compile and Download: Compile CFC charts (Changes Only) on both controllers and download changes in RUN mode.

Verification

Verify continuous communication stability through the following checks:
1. In CFC test mode on the receiving CPU, monitor Rcv_AnaVal.RcvMonErr: verify that the output remains steady at FALSE (0).
2. Monitor Rcv_AnaVal.Out.ST: confirm that the signal quality remains solid at 16#80 without periodic drops to 16#00.
3. Introduce an artificial process change at the sender input: verify that Rcv_AnaVal.Out.Value tracks the change within a single execution cycle ($500\text{ ms}$).

Limitations and Operational Precautions

Do not place Snd_AnaVal in a fast execution OB (e.g., OB35 100 ms) while placing Rcv_AnaVal in a slow execution OB (e.g., OB32 1000 ms). Mismatched OB cycle frequencies cause communication queue overflows in the CPU communication buffers. Furthermore, avoid setting CylMax = 0, as this disables the heartbeat mechanism, leaving the receiver frozen if the analog signal settles at a steady value.