Resolving Inactive Signal Forcing in SIMIT When Coupling to S7-PLCSIM

In Siemens SIMIT simulation software coupled to S7-PLCSIM, when an engineer forces a signal in the SIMIT simulation interface but the corresponding address in S7-PLCSIM remains unchanged and does not register the force state, the issue typically stems from signal direction misconfiguration in the coupling editor, continuous cyclic overwrites by controller logic in PLCSIM, or writing to process inputs without peripheral addressing. SIMIT does not activate the S7-PLCSIM GUI 'Force' table; instead, it writes cyclic process image data. To resolve the issue, verify that the signal is configured as an Output in SIMIT (which maps to a PLC Input), map the address to Peripheral Inputs (PIW/PIB) rather than internal memory (M) or outputs (Q), and ensure the SIMIT simulation engine is actively running.

Executive Summary

During virtual commissioning of PCS 7 or STEP 7 automation programs, Siemens SIMIT provides dynamic simulation of field instrumentation, valves, and drives by coupling to S7-PLCSIM. A common stumbling block for simulation engineers is observing forced signals in SIMIT that fail to affect the virtual controller. Control engineers often expect SIMIT forcing to mirror the hardware 'Force Table' of STEP 7, or they map SIMIT outputs to PLC variables that are immediately overridden by the controller's cyclic execution scan. By understanding how SIMIT's shared memory driver exchanges data with the S7-PLCSIM process image, engineers can reliably configure bidirectional signal flows and simulate field conditions.

Architecture and Fundamental Mechanics

The data exchange architecture between SIMIT and S7-PLCSIM operates on strict cyclic memory handshakes:

Coupling Memory Architecture:
* SIMIT communicates with S7-PLCSIM through a high-performance inter-process communication (IPC) shared memory buffer via the S7-PLCSIM COM/API interface.
* Data transfer is synchronous with the simulation cycle (typically 10 ms to 100 ms slices).
Signal Direction Semantics:
* In SIMIT, signal directions are defined from the perspective of the simulation model:
- Inputs to SIMIT: Data read from PLCSIM into SIMIT (PLC outputs Q, peripheral outputs PQW, memory bits M).
- Outputs from SIMIT: Data written from SIMIT into PLCSIM (PLC inputs I, peripheral inputs PIW).
- If an engineer accidentally configures a transmitter signal as an 'Input' in SIMIT, SIMIT passively listens rather than writing, preventing any signal propagation.
Cyclic Overwrite and Memory Area Arbitration:
* When SIMIT writes to an internal memory address (M) or data block (DB), that address is also accessible to the PLC ladder or CFC logic.
* If controller logic in OB1 or OB35 executes an assignment (= or MOVE) to that memory location, the PLC scan immediately overwrites the SIMIT value at the end of the scan cycle, causing the signal in PLCSIM to appear unresponsive.
Process Image vs. Peripheral Inputs:
* S7-400 and S7-410 controllers utilize Process Image Partitions (TPA) or direct peripheral addressing (PIW).
* PCS 7 APL channel drivers (Pcs7AnIn, Pcs7DiIn) read directly from peripheral addresses (PIW) rather than the process image input table (IW). If SIMIT writes only to IW, the channel driver continues reading zero counts from the unmapped peripheral area.

Step-by-Step Implementation Procedure

Follow these procedures to configure and troubleshoot active signal forcing between SIMIT and S7-PLCSIM:

Verify SIMIT Coupling Direction:
* In SIMIT, open the Couplings tree and double-click the PLCSIM coupling.
* Locate the problematic signal in the coupling table.
* Confirm the signal is placed in the Outputs section (Signals sent from SIMIT to PLCSIM).
* Verify that the data type matches the PLC declaration (BOOL for digital, INT or WORD for raw analog counts, REAL for floating point).
Map to Peripheral Addressing (PIW / PIB):
* If testing PCS 7 channel drivers, configure the address in SIMIT as peripheral input syntax (e.g., PIW 512 or PEW 512 in German mnemonics).
* Ensure the address does not conflict with local CPU work memory.
Check S7-PLCSIM Operating State:
* Open S7-PLCSIM and verify the CPU mode selector is set to RUN or RUN-P.
* Verify that the S7-PLCSIM instance index (Instance 1) matches the target instance configured in the SIMIT coupling properties.
Test Signal Injection via SIMIT Control Elements:
* In SIMIT, start the simulation by clicking the Start (Play) button in the top toolbar.
* Open a SIMIT diagram containing a manual control slider or pushbutton connected to the signal.
* Change the value in SIMIT.
* In S7-PLCSIM, open Insert > Input Variable (e.g., IW 512 or IB 0) and observe whether the bits toggle or values update dynamically.

Verification

In SIMIT, toggle a digital input signal from 0 to 1. In S7-PLCSIM, verify that the corresponding input byte in the View window reflects the bit toggle in real time. In PCS 7 CFC test mode, verify that the channel driver block (Pcs7DiIn) registers PV_In = 1 and PV_Out.Value = 1 with signal status 16#80 (Good).

Limitations and Operational Precautions

SIMIT forcing does not set the yellow 'FORCE' LED on the virtual S7-PLCSIM CPU; SIMIT injects cyclic process data rather than STEP 7 peripheral force tables. If S7-PLCSIM is stopped or paused, SIMIT coupling communication enters an error state until both environments are restarted.

Engineer FAQ

Why does no checkmark appear in the S7-PLCSIM Force column when forcing in SIMIT?

SIMIT writes cyclic process image data via the PLCSIM API; it does not manipulate the STEP 7 internal hardware Force Table which drives the PLCSIM GUI force checkboxes.

Can SIMIT write directly to controller Data Blocks (DBs)?

Yes, SIMIT can write to DB addresses, provided the DB is unlinked from controller logic that continuously overwrites those addresses during OB execution.

What happens if both SIMIT and an internal CFC block write to the same address?

The value will jitter or remain locked to the CFC block output, because the PLC cyclic scan executes immediately after the SIMIT shared memory transfer.