Resolving Intermittent Pulse Detection Failures on Digital Input Channel Drivers (Pcs7DiIn) via Process Image Partitions

In SIMATIC PCS 7, when an APL digital input channel driver (Pcs7DiIn, FB1873) intermittently misses field signal transitions visible on the physical module's channel LEDs, the cause is an unassigned or mismatched Process Image Partition (PIP) combined with cyclic interrupt scan latency. If the digital input module in HW Config is assigned to the default OB1 process image or an unassigned partition while Pcs7DiIn executes inside cyclic interrupt OB35 (e.g., 100 ms), the controller does not refresh input memory before the block executes. To resolve this, assign the module's I/O addresses to the specific Process Image Partition linked to OB35 (PIP 1), reduce the hardware input filter delay, or compile with 'Generate module drivers'.

Executive Summary

Commissioning engineers troubleshooting discrete field signals—such as limit switch pulses, proximity sensors, or push-button actuations—frequently observe that while the green channel LED on an ET 200 digital input card flickers during an actuation, the corresponding Pcs7DiIn block in CFC fails to register the change online. This gives the false impression of a defective input card or intermittent backplane bus. In reality, the S7-400 operating system decouples physical I/O updates from cyclic interrupt execution through Process Image Partitions (PIPs). If the PIP is misaligned, the input table is not updated synchronously with block execution. This guide details process image synchronization, hardware filter parameters, and the configuration steps required for reliable pulse capture.

Architecture and Fundamental Mechanics

The digital signal acquisition pipeline in SIMATIC S7-400 / CPU 410 controllers operates through three distinct synchronization gates:
1. Hardware Input Filter Delay:
Digital input modules (e.g., SM 321 or ET 200SP DI) incorporate hardware RC filters or digital debouncing filters (configurable between 0.05 ms and 20 ms, default typically 3 ms). Pulses shorter than the configured hardware delay are suppressed by the module silicon before reaching the peripheral image.
2. The Process Image Partition (PIP) Architecture:
The S7-400 operating system maintains partitioned process images:
- Default Process Image (OB1-PA): Updated cyclically only during the free-wheeling OB1 cycle.
- Process Image Partitions (TPA 1 to TPA 15 / PIP 1 to PIP 15): Bound to specific cyclic interrupt organization blocks (e.g., PIP 1 bound to OB35, PIP 2 bound to OB32).
When an OB executes, the operating system reads the peripheral inputs belonging to that partition immediately before calling the first block in the OB.
3. The Channel Driver Sampling Mismatch:
In PCS 7, Pcs7DiIn executes inside cyclic interrupt OB35 (default 100 ms). If the module in HW Config is left in the default OB1 partition, the input memory is not refreshed when OB35 runs. Pcs7DiIn reads stale memory, completely missing fast field pulses that occur between slow OB1 cycles.

Step-by-Step Implementation Procedure

Verify Cyclic Interrupt Assignment in CFC:
a. Open the CFC chart containing the Pcs7DiIn channel driver block.
b. Check the runtime properties of the block: confirm which cyclic interrupt OB executes the block (typically OB35 with cycle time 100 ms or OB36 with 50 ms).
Configure Process Image Partition in HW Config:
a. Open STEP 7 HW Config for the AS station.
b. Double-click the digital input module in the rack (e.g., DI 16xDC 24V).
c. In the 'Addresses' tab, locate the 'Process image' dropdown.
d. Change the selection from 'OB1-PA' or '---' to the partition corresponding to the block's OB (e.g., 'PIP 1' for OB35).
e. In the 'Parameters' tab, inspect the 'Input delay' (Hardware filter): reduce it from 3 ms or 16 ms to 0.5 ms or 1 ms if capturing high-speed sensor pulses.
Execute Automated Module Driver Generation:
a. In SIMATIC Manager, select the Charts folder.
b. Execute Chart -> Compile -> Chart as Program....
c. Ensure the checkbox 'Generate module drivers' is checked.
d. When driver generation runs, the PCS 7 compiler inspects HW Config and automatically harmonizes the module's PIP assignment with the execution OB of the interconnected Pcs7DiIn block.
Download Hardware and Program Changes:
a. Save and compile HW Config.
b. Download the updated hardware configuration and CFC program to the AS controller.

Verification

In CFC Test Mode, monitor input parameter PV_In and output PV_Out on Pcs7DiIn.
Actuate the field sensor: observe the green LED on the physical card.
Confirm that PV_Out.Value transitions from 0 to 1 synchronously in CFC without missed pulses.
If measuring pulses near the cycle limit (e.g., 80 ms pulses on a 100 ms OB), consider moving the channel driver to a faster cyclic OB (e.g., OB36 at 50 ms) or using hardware pulse-stretching inputs.

Limitations and Operational Precautions

Assigning too many high-density I/O modules to fast cyclic interrupt partitions (such as OB36 at 50 ms or OB38 at 10 ms) increases CPU scan overhead and can trigger cycle time overruns; assign only pulse-critical signals to fast partitions.

Engineer FAQ

Why did the module LED turn ON but the CFC block didn't see it?

The module's physical LED responds directly to electrical voltage at the terminal, whereas the CFC block reads process image memory. If the Process Image Partition is not refreshed before the OB runs, the pulse is missed.

What is a Process Image Partition (PIP) in S7-400?

A PIP is a subset of the controller process image that is updated synchronously at the start of a specific cyclic interrupt OB (such as OB35), rather than during the slower OB1 cycle.

How do I know which PIP is assigned to which OB?

In HW Config, open CPU Properties -> 'Cycle/Clock Memory' tab: the table lists the binding between Organization Blocks (OB30-OB38) and Process Image Partitions (PIP 1-15).

Can input delay filters on the card cause missed pulses?

Yes. If the hardware input delay is configured to 16 ms, any sensor pulse shorter than 16 ms is discarded by the module's input circuitry as electrical noise.

What should I do if a pulse is shorter than 50 ms?

Use digital input modules with integrated pulse stretching (e.g., ET 200SP High Feature DI cards with pulse capture), or wire the signal to a fast counter / interrupt module.