Resolving Module Driver Generation Errors during Migration from PCS 7 V8.0 to V9.0

When 'Generate module drivers' fails during CFC compilation following a project migration from PCS 7 V8.0 SP1 to V9.0 SP2, the failure is caused by library family mismatches between legacy channel blocks ('AdvLib80') and the newly installed Basis Library ('AdvLib90'). The V9.0 compiler attempts to generate modern '@' diagnostic blocks that have incompatible structural interfaces with older V8.0 blocks remaining in the chart folder. To resolve this, either update all chart blocks to the V9.0 library family via 'Options > Block Types > Update', or install the legacy PCS 7 Basis and APL library packages on the V9.0 Engineering Station.

Executive Summary

Migrating an automation software project across multiple major versions—such as upgrading from SIMATIC PCS 7 V8.0 SP1 to V9.0 SP2—is a complex engineering lifecycle task. A frequent post-migration obstacle occurs when the user program and hardware configuration appear to compile cleanly, but executing CFC compilation with 'Generate module drivers' throws fatal compiler errors. This article examines the architectural conflict between legacy AdvLib80 block interfaces and modern V9.0 module driver generator rules, and provides the step-by-step procedure to resolve driver generator errors using block type modernization or legacy library retention.

Architecture and Fundamental Mechanics

Architectural Mechanics of Module Driver Generation during Version Migration:

Role of the Module Driver Generator:
During CFC compilation with 'Generate module drivers' enabled, the PCS 7 compiler reads hardware addresses from HW Config and cross-references them with channel blocks (Pcs7AnIn, Pcs7DiIn, Pcs7AnOu, etc.) in the chart folder.
It automatically creates @ system diagnostic charts containing diagnostic blocks (CH_AI, MOD_D1, RACK, OB_BEGIN) that monitor module health, passivation, and fieldbus diagnostics.
The Root Cause of Migration Driver Compilation Errors:
In PCS 7 V8.0 SP1, channel drivers and system diagnostic blocks belong to the AdvLib80 (APL V8.0) and Basis Library V8.0 family.
PCS 7 V9.0 SP2 installs AdvLib90 (APL V9.0) and Basis Library V9.0 by default on the Engineering Station.
When an older project is migrated into V9.0, the chart folder retains the compiled V8.0 block headers.
During compilation, the V9.0 Module Driver Generator attempts to interconnect newly generated V9.0 diagnostic blocks with older V8.0 channel blocks. Because internal structural pins (Mode, DataXchg, MS) underwent structural interface changes between V8.0 and V9.0, the compiler aborts with parameter mismatch errors.
Two Approved Siemens Migration Strategies:
1. Block Type Modernization (Full Upgrade - Recommended):
- Updates all library blocks in the project to the latest V9.0 versions (AdvLib90). Ensures long-term maintainability and access to new hardware (e.g. ET 200SP HA).
- Constraint: Modifying block interfaces changes block timestamps, requiring a full AS compilation and an AS STOP download (unless using CPU 410-5H Type Change in RUN - TCiR).
  2. Migration with Retained Library Versions (Without Block Upgrade):
- If plant operational constraints prohibit an AS STOP, the engineer must install the PCS 7 Legacy / Additional Libraries on the V9.0 ES. This allows the V9.0 compiler to generate matching V8.0 module drivers without altering block interfaces.

Step-by-Step Implementation Procedure

Step-by-Step Procedure to Resolve Module Driver Generation Errors:

Strategy A: Complete Block Modernization to APL V9.0 (Recommended):
1. Update Master Data Library:
- Open the Master Data Library in SIMATIC Manager.
- Copy the latest blocks from the PCS 7 APL V9.0 library (AdvLib90) and PCS 7 Basis Library V9.0 into the Master Data Library Blocks folder.
2. Update Block Types in the S7 Program:
- Open any CFC chart in the project.
- Select menu Options -> Block Types.
- In the Block Types dialog, select all channel blocks (Pcs7AnIn, Pcs7DiIn, Pcs7AnOu, etc.) and technological blocks.
- Click the Update... button.
- Acknowledge that block interfaces will be updated across all charts.
3. Recompile Charts with Module Driver Generation:
- In the CFC editor, select Chart -> Compile -> Charts as Program.
- Select Scope: Entire program.
- Enable checkbox: Generate module drivers.
- Complete compilation; verify zero errors.

Strategy B: Retaining Legacy V8.0 Block Versions (When AS STOP is Prohibited):
1. Install Legacy Additional Libraries on ES:
- Insert the official Siemens PCS 7 Additional Libraries / Legacy DVD (or download from SIOS Entry ID 109480136).
- Install the legacy PCS 7 Basis Library V8.0 SP1 on the PCS 7 V9.0 Engineering Station.
2. Verify Library Registration in SIMATIC Manager:
- Open File -> Open -> Libraries; verify that PCS 7 Basis Library V80 is listed.
3. Recompile CFC Charts:
- In CFC, select Chart -> Compile -> Charts as Program (Entire program) with Generate module drivers enabled.
- The compiler uses the legacy driver generator templates, matching the unchanged V8.0 channel blocks on the charts.

Verification

Verification Procedure:
1. Compilation Log Verification: Inspect the CFC compilation log. Verify that compilation finishes with 0 Errors and confirming system charts (@...) were generated successfully.
2. System Chart Inspection: Open an auto-generated system chart @(1). Verify that driver blocks (CH_AI, MOD_D1) are cleanly interconnected to hardware diagnostic addresses without broken lines.
3. Channel Quality Check: In CFC Test Mode, open Pcs7AnIn. Verify that output PV_Out.ST indicates 16#80 (Good) and matches live physical process signals.

Limitations and Operational Precautions

Operational Precautions and Migration Constraints:
- AS STOP Warning for Block Updates: Modernizing block types changes interface timestamps. On standard S7-400 CPUs, this strictly requires downloading the user program in STOP mode.
- CPU 410-5H Type Change in RUN (TCiR): If operating CPU 410-5H controllers, block type updates can be downloaded in RUN mode, provided offline memory headroom and TCiR constraints are observed.
- Never mix incompatible channel driver versions (e.g. Pcs7AnIn from V8.0 with MOD_D1 from V9.0) in the same S7 program.

Engineer FAQ

Why did module driver generation fail after migrating to PCS 7 V9.0?

Because the chart folder still contained legacy V8.0 channel blocks (AdvLib80) whose internal pin interfaces conflict with the newly installed V9.0 Basis Library driver generator.

How do I update all channel blocks to the latest V9.0 library version?

Open any CFC chart, select Options -> Block Types, select the channel blocks, and click Update....

Can I compile a migrated V8.0 project in V9.0 without updating blocks?

Yes, by installing the official Siemens PCS 7 Additional Libraries (Legacy) package containing the older V8.0 Basis Library onto the V9.0 Engineering Station.

Does updating block types require stopping the controller?

On standard S7-400 CPUs, yes, updating block types requires an AS download in STOP. On CPU 410-5H, Type Change in RUN (TCiR) can be used to update blocks in RUN mode.