Resolving Timer and Ramp Gradient Double-Count Discrepancies in S7-400H Controllers

In SIMATIC PCS 7, timers, sequence step transitions, and setpoint ramp gradients counting at double or half speed following an S7-400H CPU firmware upgrade (e.g., to V4.5.7) are caused by a discrepancy between the cyclic interrupt Organization Block (OB) execution period and the block's internal 'SampleTime' parameter. This desynchronization occurs when cyclic interrupt OB cycle times or Process Image Partition (PIP) assignments are altered in HW Config without performing a full chart compilation, or when CFC runtime group reduction ratios are misconfigured.

Executive Summary

Following firmware upgrades or major hardware configuration changes on SIMATIC S7-400H controllers (such as migrating CPU 417-4H or CPU 410-5H to newer microcode revisions), engineers may observe severe time-dilation anomalies in process control logic. Symptoms include analog ramp functions (RampP, PIDConL setpoint ramps) taking exactly twice as long to reach setpoints, sequence timers (TimerP, Timer_P) counting at half or double speed, and valve travel monitoring times elapsing prematurely.

While engineers frequently suspect internal CPU microcode or operating system firmware defects, the root cause is almost invariably algorithmic: PCS 7 block timers do not interrogate the CPU's real-time hardware clock cyclically. Instead, they integrate time numerically by adding the block's SampleTime parameter upon each execution invocation. If the calling Organization Block's actual execution interval deviates from the parameter value stamped into the block, numerical time integration diverges linearly. This article breaks down the timing mechanics of PCS 7 CFC execution, analyzes the impact of PIP and runtime group reduction factors, and provides exact recovery steps.

Architecture and Fundamental Mechanics

The mathematical foundation of time calculation in the PCS 7 Advanced Process Library (APL) and Standard Library relies on discrete-time integration. Blocks such as TimerP, RampP, MotL, and PIDConL calculate elapsed time according to the formula:

Accumulated_Time = Accumulated_Time + SampleTime

The Role of the Organization Block: In standard PCS 7 architectures, continuous control logic is executed within cyclic interrupt Organization Blocks (OB30 through OB38). By default, OB35 is configured to trigger every 100 ms (0.10 s).
The Role of the SampleTime Parameter: When a CFC chart is compiled, the PCS 7 compiler inspects the cyclic OB where the block's runtime group is scheduled. If scheduled in OB35 (100 ms), the compiler automatically initializes the hidden or visible input parameter SampleTime (or SAMPLE_T) to 0.100 seconds. If scheduled in OB32 (1000 ms), it sets SampleTime to 1.000 seconds.
Causes of Timing Doubling Discrepancies:
- HW Config Modification Without CFC Recompile: If an engineer or firmware migration alters the OB35 cycle interval in HW Config from 100 ms to 200 ms, the CPU now executes the block half as frequently (5 times per second instead of 10). However, if CFC charts are not fully recompiled with 'Generate module drivers', the blocks retain SampleTime = 0.100s. Consequently, every second of real-world wall-clock time yields only 0.5s of accumulated integration time—causing timers to count at double duration!
- Runtime Group Reduction Ratios: In the CFC Runtime Editor, each runtime group possesses a 'Reduction ratio' and 'Phase offset'. If a runtime group scheduled in OB35 is accidentally assigned a reduction ratio of 2 (executing every second invocation of OB35, or every 200 ms), but SampleTime remains 0.1s, time accumulation runs at half speed.
- Process Image Partition (PIP) Updates: If I/O modules assigned to a specific PIP are synchronized with an OB whose execution cycle was altered, driver blocks and connected timers experience skewed execution timing.

Step-by-Step Implementation Procedure

Follow these steps to diagnose and correct timer and ramp gradient double-count discrepancies in S7-400H controllers:

Verify Cyclic Interrupt OB Cycle Times in HW Config:
- In SIMATIC Manager, open HW Config for the affected S7-400H station.
- Double-click the active CPU (e.g., CPU 417-4H or CPU 410-5H) to open 'Properties'.
- Navigate to the 'Cyclic Interrupts' tab.
- Review the configured execution period for each active OB (e.g., OB35 default 100 ms, OB34 default 200 ms, OB32 default 1000 ms).
- Confirm that OB execution times match standard plant baseline settings.
Inspect Block Scheduling in the CFC Runtime Editor:
- Open any CFC chart containing a misbehaving timer or ramp block.
- Select the block and press Ctrl+E (or select 'Options > Edit Run Sequence...') to launch the Runtime Editor.
- Locate the runtime group containing the block.
- Inspect the assigned Organization Block (e.g., OB35).
- Check the 'Reduction ratio' and 'Phase' properties for the runtime group. Verify that the reduction ratio is set to 1 (unless deliberate reduction was planned and accounted for).
Verify the SampleTime Parameter Value on the Block:
- In the CFC chart, select the affected block (e.g., TimerP or RampP).
- Open block properties (double-click the block header or right-click > 'Object Properties').
- Switch to the 'I/Os' tab and locate the input parameter SampleTime (or SAMPLE_T).
- Verify that the value matches the actual calling period: if called in OB35 at 100 ms, SampleTime must equal 0.1 (seconds). If the value is 0.05 or 0.2, numerical drift occurs.
- Ensure the parameter is not interconnected to an incorrect dynamic variable or overridden by manual logic.
Execute a Full CFC Compilation:
- In SIMATIC Manager, select the Charts folder in the S7 Program hierarchy.
- Select 'PLC > Compile > Charts as Program...'.
- In the compilation dialog, select 'Entire program' (do NOT select 'Changes only').
- Check the box 'Generate module drivers'.
- Click 'OK'. The PCS 7 compiler re-evaluates all OB execution intervals in HW Config and automatically updates the SampleTime attributes across every block instance.
Download Program Changes to Controller in RUN:
- Once compilation finishes without errors, select 'PLC > Download > Download to target system...'.
- Download the program changes to the S7-400H controller. In redundant H-systems, this download executes smoothly in RUN mode without stopping the plant.

Verification

In CFC test mode (online monitoring), open the affected timer block and observe the accumulated time output (Time or Out) alongside a physical stopwatch.
Trigger a 60-second timer countdown or ramp gradient change.
Verify that 60 seconds on the stopwatch correspond to exactly 60.0 seconds of accumulated time on the controller block.
Check the CPU Diagnostic Buffer to verify zero OB overrun entries (Event ID 16#3501 or 16#3502 indicating OB cycle execution overruns).
Test operator faceplate ramp commands to confirm expected ramp-up and ramp-down rates in engineering units per minute.

Limitations and Operational Precautions

Changing cyclic interrupt OB execution periods in HW Config requires downloading hardware configuration changes, which in non-H controllers requires a CPU STOP. In redundant S7-400H / CPU 410-5H systems, HW Config updates can be performed in RUN mode using Configuration in Run (CiR), provided valid CiR objects exist. Never manually hardcode static SampleTime values on blocks that can be shifted across different cyclic OBs. Verify all hardware, firmware, and upgrade requirements with an authorized Siemens distributor or the Siemens Industry Mall.

Engineer FAQ

Why did upgrading CPU firmware trigger this timing problem?

Upgrading CPU firmware in STOP mode often prompts engineers to re-read or re-import hardware configurations from newer catalog definitions, which can inadvertently reset or alter cyclic interrupt execution times from custom settings back to defaults.

Can I fix this by simply changing SampleTime on individual blocks?

While changing SampleTime manually adjusts that specific block, it does not fix the root cause. A full compilation of 'Charts as Program' ensures all blocks in the program are synchronized with the true OB cycle times.

What happens if a cyclic OB execution takes longer than its configured time?

If the program logic inside OB35 takes longer than 100 ms to execute, the CPU triggers a time-error interrupt (OB80). If OB80 is missing, the CPU enters STOP mode. If OB80 is present, the CPU skips or delays cycles, causing timing drift.

Does Process Image Partition (PIP) affect timer counting?

PIP governs when I/O signals are updated from physical modules. While PIP updates do not alter the math of SampleTime, assigning inputs to a PIP that runs in a slower OB can cause delayed edge detection, mimicking timing lag.

How does APL RampP handle gradient timing?

APL RampP uses SampleTime to increment the setpoint step on each execution call: Step = Gradient * SampleTime. If SampleTime is misaligned with the actual execution rate, the ramp speed doubles or halves.