Understanding APL Structured Data Types and Eliminating Data Type Conflicts in PCS 7 CFC

In SIMATIC PCS 7 Advanced Process Library (APL), attempting to eliminate structured data types from CFC block pins to connect raw elementary addresses (such as BOOL, INT, or REAL) directly from the Symbol Table is fundamentally incompatible with PCS 7 architecture. APL technological blocks require composite structures (containing both the engineering Value and an integrated NAMUR NE107 Signal Status byte ST) to propagate measurement quality and failure diagnostics from field devices to operator faceplates. Rather than modifying or stripping block interfaces, standard PCS 7 engineering bridges elementary hardware addresses and technological structures using APL channel driver blocks (such as Pcs7DiIn or Pcs7AnIn) or lightweight structure converters (StruDiOu or StruAnOu).

Executive Summary

Engineers familiar with classical PLC environments (STEP 7 V5.x or TIA Portal) often find the structured data types of the PCS 7 Advanced Process Library restrictive when trying to wire signals in CFC. Attempting to connect simple input bits (I0.0) or memory words (MW100) directly to technological blocks results in CFC type mismatch errors. To circumvent this, some engineers consider editing library block declarations to replace structures with elementary types. This practice invalidates the PCS 7 system architecture. In APL, structured signals are mandatory because they carry critical operational quality codes alongside numerical values. Understanding how channel drivers and structure conversion functions operate ensures full compliance with PCS 7 DCS design standards.

Architecture and Fundamental Mechanics

The design rationale and data exchange mechanics of APL structured data types operate through specific systemic functions:

The Composition of an APL Structure:
* An APL digital structure (Struct) encapsulates:
- .Value : BOOL (The boolean state of the process parameter).
- .ST : BYTE (The signal status byte adhering to NAMUR NE107).
- An APL analog structure encapsulates:
- .Value : REAL (Floating-point engineering measurement).
- .ST : BYTE (Quality code byte).
Why Elementary Types Fail in DCS Environments:
* A simple BOOL or REAL carries no metadata regarding the physical health of the transmitter, the status of power supplies, or whether the signal is currently in simulation.
* If a wire breaks on a 4..20 mA flow transmitter, an elementary REAL simply reads 0.0, which a downstream PID controller might interpret as valid low flow, opening a control valve to 100% and causing a vessel overflow.
* In contrast, an APL structure sets ST = 16#28 (Bad, device-related). Downstream controllers immediately detect this degraded status, shedding to manual or safe track mode without human intervention.
The Channel Driver Bridge:
* Channel driver blocks (Pcs7DiIn, Pcs7DiOu, Pcs7AnIn, Pcs7AnOu) are the dedicated structural transformers in PCS 7.
* They take raw hardware addresses (I0.0, PIW 512) on their inputs and output fully qualified APL structures (PV_Out) enriched with diagnostic data from the Basis Library.
Structure Conversion Utilities:
* When non-channel signals (internal state flags or auxiliary calculations) must interface with APL blocks, structure composer and decomposer functions provide clean conversion:
- StruDiOu (FC 378): Packs elementary BOOL + BYTE into an APL digital structure.
- StruAnOu (FC 376): Packs elementary REAL + BYTE into an APL analog structure.
- StruDiIn (FC 377): Unpacks an APL digital structure into elementary BOOL + BYTE.
- StruAnIn (FC 375): Unpacks an APL analog structure into elementary REAL + BYTE.

Step-by-Step Implementation Procedure

Follow these procedures to connect physical hardware addresses and non-structured signals to APL blocks without altering block interfaces:

Method 1: Connect Physical I/O via Channel Drivers (Standard DCS Architecture):
* In SIMATIC Manager HW Config, ensure all I/O channels are symbolically named in the Symbol Table.
* In CFC editor, drag Pcs7DiIn (for digital inputs) or Pcs7AnIn (for analog inputs) from Libraries > PCS 7 AP Library > Channel into the chart.
* Connect the hardware symbol or address (I0.0 or IW 512) to the channel driver's input pin PV_In using Interconnection to Address....
* Connect the structured output pin PV_Out to the destination technological block input (e.g., MotL.FbkRun or PidConL.PV).
* During CFC compilation, check Generate module drivers to automatically link Basis Library diagnostic blocks.
Method 2: Convert Elementary Signals via StruDiOu / StruAnOu (Auxiliary Signals):
* In CFC editor, open Libraries > PCS 7 AP Library > Structure.
* Drag StruDiOu (FC 378) or StruAnOu (FC 376) into the chart.
* Connect your elementary boolean bit or memory address to the Value input.
* Configure the ST (Signal Status) input to 16#80 (representing Good status).
* Connect the structured output pin Out directly to the APL block input.
Method 3: Deconstruct APL Structures to Drive Physical Outputs:
* To drive an elementary physical coil (Q0.0) from an APL block output:
* Insert Pcs7DiOu (FB 1868), connect the technological block output to PV_In, and connect PV_Out to Q0.0.
* Alternatively, insert StruDiIn (FC 377), connect the APL output to In, and connect Value to Q0.0 via Interconnection to Address....

Verification

In CFC editor, switch to Test Mode (online). Verify that the structured connection displays a healthy green line. Confirm that the technological block reads both the live .Value and a valid signal status (ST = 16#80). Disconnect the physical sensor or simulate a wire break in HW Config; verify that the channel driver immediately degrades ST to 16#28 (Bad), causing the technological block faceplate in WinCC to display a yellow diagnostic warning glyph.

Limitations and Operational Precautions

Never modify official APL library block declarations (FBs) to replace structured pins with elementary types; doing so breaks AS-OS compilation, invalidates WinCC faceplate communication, and makes future library updates impossible. Always use standard channel drivers for plant safety and process interlocking signals.

Engineer FAQ

Why should I not modify APL block interfaces to remove structures?

Altering APL block interfaces causes AS-OS compilation failures, corrupts WinCC faceplate scripts, disables automated module diagnostics, and prevents applying official Siemens library patches.

What is the difference between Pcs7DiIn and StruDiOu?

Pcs7DiIn is a full channel driver that links to hardware diagnostic blocks (monitoring module health and wire breaks); StruDiOu is a simple math conversion function that packages a boolean and a static status byte without hardware monitoring.