C135 PCS 7 (PCS7)
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Understanding P_Rst Output Trigger Conditions and Reset Interlocks in APL MotVarL

Understanding P_Rst Output Trigger Conditions and Reset Interlocks in APL MotVarL

In the SIMATIC PCS 7 Advanced Process Library (APL) MotVarL (Variable Speed Motor) block, the P_Rst output generates a single-cycle pulse to acknowledge external physical drive faults only when the block accepts a valid reset request (RdyToReset = 1). P_Rst will not trigger if RdyToReset = 0. Resetting is prevented if the underlying fault or interlock (LockAct = 1, Trip = 1) remains physically active, if the motor is in Local mode without release (LocalAct = 1), or if manual reset is disabled by Feature.Bit31 ('Reset can be completed in manual mode'). The fault condition must clear before a reset command at RstOp or RstLi executes.

Table of Contents

Executive Summary

During commissioning and testing of variable-speed drive systems in SIMATIC PCS 7, engineers frequently observe that clicking the 'Reset' button on a WinCC faceplate or setting the RstLi (interconnected reset) input in CFC fails to produce an output pulse at P_Rst. In many instances, the faceplate reset button is disabled (greyed out) or displays a yellow 'S' simulation/error badge. This issue occurs because the PCS 7 Advanced Process Library (APL) enforces strict deterministic reset interlocking on the MotVarL block (FB1854). The block asserts P_Rst only when a valid fault state exists and has been successfully cleared, the controller is in a permissive operating mode, and RdyToReset evaluates to 1. Understanding this internal finite-state logic is essential for correctly interfacing APL motor blocks with variable-frequency drives (VFDs).

Architecture and Fundamental Mechanics

The MotVarL block manages operational commands, speed setpoints, feedback monitoring, and fault handling for variable-speed drives. The P_Rst output is specifically designed to energize a physical digital output (via Pcs7DiOu) connected to the VFD's digital reset terminal.

1. The RdyToReset Evaluation Logic

The P_Rst pulse output cannot trigger spontaneously. The internal APL algorithm evaluates whether the block is ready to receive a reset command, represented by the output RdyToReset. For RdyToReset to become 1:
- A resettable fault condition must have occurred (e.g., feedback monitoring error MonDynErr, MonStaErr, or external trip Trip = 1).
- The root fault condition must no longer be present at the input terminals. If Trip remains 1 or an interlock input (Intlock, Protect, Permit) is still asserted (LockAct = 1), RdyToReset remains 0.
- In Local mode (LocalAct = 1), reset commands from the OS faceplate (RstOp) or automatic logic (RstLi) are ignored unless local operation allows remote reset.

2. Feature Bit Dependencies (Feature.Bit30 and Feature.Bit31)

APL introduces configurable behavioral rules via the Feature parameter word:
- Feature.Bit30 (Resetting depending on operating mode): Defines whether resetting is allowed in Manual mode, Automatic mode, or both.
- Feature.Bit31 (Resetting can be completed in manual mode): If Feature.Bit31 = 0, a reset can only be executed in Automatic mode via RstLi. If Feature.Bit31 = 1, an operator can execute a reset directly from the WinCC faceplate (RstOp) while in Manual mode.
- When an accepted reset pulse arrives while RdyToReset = 1, MotVarL outputs a boolean pulse of exactly one CPU execution cycle (SampleTime) at P_Rst and clears the internal error latches (GrpErr = 0).

Step-by-Step Implementation Procedure

To diagnose and resolve stuck reset conditions on MotVarL:

Step 1: Inspect Error and Interlock Status in CFC Online

  1. Open the CFC chart containing the MotVarL instance and switch to Test Mode (Online).
  2. Inspect the block's interlocking status flags:
    - LockAct: If LockAct = 1, an interlock condition is active. Trace connections to Intlock, SupInt, or Protect. The interlock must clear before resetting.
    - Trip: Verify that the VFD fault input Trip has returned to 0 (normal state).
    - LocalAct: If LocalAct = 1, the block is locked in Local mode. Switch LocalSetting or release local control.

Step 2: Verify and Configure Feature Bits

  1. Check the parameter Feature on the MotVarL block:
    - To allow operator reset from the WinCC faceplate during Manual mode, ensure Feature.Bit31 = 1 ('Reset can be completed in manual mode').
    - If resetting must be performed automatically via CFC logic, verify that RstLi receives a $0 \rightarrow 1$ positive edge pulse while the motor is in Automatic mode.

Step 3: Verify RdyToReset and Execute Reset

  1. Once the physical fault has cleared and mode permissions are satisfied, verify that output RdyToReset = 1.
  2. If RdyToReset = 1, trigger the reset:
    - From WinCC: Open the MotVarL faceplate and click the 'Reset' button (now active).
    - From CFC: Set input RstLi to 1 for one scan cycle.
  3. Verify that P_Rst pulses high for one cycle and resets the connected digital output channel.

Verification

To verify proper reset operation:

  1. CFC Online Signal Trace:
    - In CFC Test Mode, simulate a feedback fault (MonDynErr = 1). Confirm GrpErr = 1 and RdyToReset = 0.
    - Restore normal feedback. Confirm RdyToReset transitions from 0 to 1.
    - Pulse RstLi to 1. Confirm that GrpErr transitions to 0, RdyToReset resets to 0, and the drive fault clears.

  2. Faceplate Reset Verification:
    - Verify that the WinCC faceplate reset button highlights and enables when RdyToReset = 1.
    - Click the Reset button and verify that the yellow 'S' / alarm badge clears immediately.

Limitations and Operational Precautions

Operational limitations and precautions:

  1. One-Cycle Pulse Duration: Because P_Rst is high for only one CPU execution cycle (e.g., 100 ms in OB35), physical relay outputs or slow VFD optocoupler inputs may fail to capture extremely brief pulses. If the drive requires a longer reset pulse (e.g., 500 ms), cascade a PulseP or TimerP block after P_Rst.
  2. Simulation Mode Behavior: When SimOn = 1, the block operates in internal software simulation. Reset interlocking rules still apply; simulating an error without clearing simulated inputs will not allow RdyToReset to assert.
  3. Rapid Stop Active: If RapidStp = 1, reset is locked out until the emergency rapid stop condition is explicitly removed.
  4. Commercial Disclaimer: Verify all APL library versions, drive integration packages, and engineering tools with an authorized Siemens distributor or the Siemens Industry Mall.

Engineer FAQ

Why is the faceplate reset button greyed out on MotVarL?

The button is greyed out because the block's RdyToReset output is 0. This occurs if an active fault still exists, an interlock (LockAct = 1) is active, or Feature.Bit31 does not allow manual reset.

Why didn't forcing RstLi = 1 trigger the P_Rst output?

RstLi is only evaluated when the block is in Automatic mode and RdyToReset = 1. Forcing RstLi while the block is in Manual mode or while an interlock is active produces no effect.

What is the duration of the P_Rst output pulse?

P_Rst remains active for exactly one CPU execution cycle corresponding to the cyclic interrupt OB where MotVarL is scheduled (typically 100 ms in OB35).

How do I configure MotVarL to allow faceplate reset in Manual mode?

Set Feature.Bit31 = 1 on the MotVarL block instance. This permits the operator to acknowledge faults via RstOp when the block is in Manual mode.

What does the yellow 'S' symbol mean on the APL faceplate?

A yellow 'S' indicates that simulation is active (SimAct = 1 or SimOn = 1) on the block or on one of its interconnected channel driver blocks.

Technical References

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Related Tags

  • MotVarL
  • APL Reset
  • P_Rst
  • Interlocking
  • Variable Speed Motor
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