Understanding S7-400 and CPU 410 Cyclic Interrupt Preemption, OB Priorities, and Phase Offset in PCS 7

In SIMATIC S7-400 and CPU 410 controllers, Organization Blocks (OBs) operate under a preemptive priority-based scheduling model. When a higher-priority cyclic interrupt (e.g., OB35 at priority 14) is triggered while a lower-priority interrupt (e.g., OB37 at priority 13) is executing, the CPU immediately pauses the lower-priority OB, preserves its accumulator registers and local stack, executes the higher-priority OB to completion, and then resumes the lower-priority OB exactly where it stopped. To prevent cycle overruns (OB80) caused by concurrent execution peaks, engineers configure Phase Offset in HW Config to stagger OB start times across basic clock cycles.

Preemptive Priority-Based Scheduling Architecture in S7-400 Controllers

SIMATIC S7-400 and CPU 410-5H automation stations execute control logic within Organization Blocks (OBs) managed by a real-time operating system kernel. Unlike simple PLCs that execute a single continuous scanning loop, S7-400 controllers employ preemptive, priority-driven multitasking.

Every Organization Block is assigned an execution priority class (ranging from 1 to 28):
* Priority 1 represents the baseline background cycle (OB1).
* Priorities 2 through 24 govern cyclic interrupts (OB30 through OB38), time-of-day interrupts, delay interrupts, and asynchronous event tasks.
* Priorities 25 through 28 govern critical hardware and system fault routines (such as peripheral access faults OB122 or diagnostic alarms OB82).
* When multiple OBs are scheduled simultaneously, the CPU scheduler evaluates their priority numbers: the task with the higher numerical priority always preempts tasks with lower numerical priorities.

Execution Behavior: Pausing, Context Switching, and Resumption

A frequent question among control engineers is what occurs when an active cyclic interrupt is preempted:

Scenario: Suppose OB37 is configured for a 10 ms interval at priority 13 (execution time ~1 ms), and OB35 is configured for a 100 ms interval at priority 14 (execution time ~35 ms).
Preemption Event:
1. While OB37 is actively executing, the 100 ms timer for OB35 expires.
2. Because OB35 has priority 14 (higher than 13), the CPU executes an immediate context switch.
3. The operating system kernel saves the program counter, accumulator registers (ACCU1, ACCU2), status register, and local data stack of OB37 into memory.
4. The CPU transfers execution to OB35, which executes for 35 ms.
5. Once OB35 finishes (BE instruction), the scheduler restores the context of OB37.
6. OB37 resumes execution from the exact instruction where it was interrupted and runs to completion.
Important Preemption Rule: The pending program in the lower-priority OB is never aborted or restarted; it is paused and resumed seamlessly.

Cycle Time Overruns and Time Error Handling (OB80)

A critical constraint in cyclic interrupt architecture is that every OB must finish execution before its next scheduled interval expires:

If an OB execution takes longer than its configured time interval—or if preemption by higher-priority tasks delays its completion past its next trigger point—a Time Error occurs.
When this occurs, the CPU does not abort the task; instead, it immediately triggers OB80 (Time Error Organization Block).
CPU Protection Mechanism:
If OB80 is programmed in the CPU, the controller executes the error handling logic in OB80 and allows the delayed cyclic interrupt to complete later.
If OB80 is missing from the CPU block folder, the CPU immediately drops into STOP mode to protect the process from executing with stale data.
If a second consecutive time error occurs on the same OB before the first can recover, the CPU enters STOP mode regardless of OB80.

Configuring Phase Offset to Stagger Cyclic Interrupt Execution

In large PCS 7 projects with thousands of CFC blocks distributed across multiple cyclic tasks (OB35 @ 100ms, OB34 @ 200ms, OB33 @ 500ms, OB32 @ 1000ms), an execution spike occurs whenever the intervals coincide (e.g., at the 1-second mark, all cyclic OBs are triggered at the same moment).

To flatten CPU execution loads and prevent OB80 time error overruns, configure Phase Offset:
1. Open HW Config and open the Properties of the CPU.
2. Select the Cyclic Interrupts tab.
3. For each OB, review the interval and configure a Phase Offset:
* The phase offset delays the start of an OB by a specified number of basic clock cycles after the interval expires.
* Formula: Phase Offset = m * Basic Clock Rate (where 0 <= m < n).
* Example: For OB35 (100 ms) and OB34 (200 ms), offset OB35 by 0 ms and offset OB34 by 50 ms. This ensures their execution peaks never coincide on the same CPU clock cycle.
4. Save and compile HW Config, and download the configuration to the CPU.

Comparison of PCS 7 Cyclic Interrupt Organization Blocks

The table below outlines the standard cyclic interrupt organization blocks used in SIMATIC PCS 7, their default intervals, and typical application domains.

Organization BlockDefault IntervalDefault PriorityPrimary PCS 7 Application DomainOB3810 ms12High-speed fast drives, turbine trip interlocksOB3720 ms13Fast analog loops, hydraulic positioningOB3650 ms14Standard motor control, interlocked digital logicOB35100 ms15Standard PID controllers, flow and pressure loopsOB34200 ms16Slow temperature loops, level controllersOB33500 ms17Analytical measurements, batch phase supervisionOB321000 ms (1 s)18Totalizer accumulation, environmental reportingOB312000 ms (2 s)19Tank volume calculations, slow supervisory tasksOB305000 ms (5 s)20Long-term diagnostic checks, statistics logging

Verification

To confirm proper cyclic interrupt execution and absence of time errors:
1. In SIMATIC Manager, select the CPU and open PLC > Module Information.
2. Inspect the Cycle Time tab: verify that the scan time remains stable well below the maximum configured cycle time.
3. Open the Diagnostic Buffer tab: confirm there are zero entries for Event ID 16#3501 or 16#3502 (Cycle time exceeded / Time error).
4. In CFC, open Chart > Reference Data > Run Sequence. Verify that block execution runtimes within each OB do not exceed 60% of the OB interval.
5. In HW Config, verify that Phase Offset values are staggered across all active cyclic interrupt OBs.

Limitations and Operational Precautions

Never set an OB execution priority higher than diagnostic fault OBs (priorities 25-28); delaying fault routines can prevent the CPU from responding to emergency rack power failures.
In PCS 7, do not alter default OB execution frequencies and priorities unless strictly necessary for process dynamics, as PCS 7 driver blocks and APL controllers are tuned for standard sampling intervals.
Always ensure OB80 is loaded in the CPU block folder; omitting OB80 guarantees that a single transient execution spike will trip the entire controller into STOP mode.
The sum of execution times of all high-priority OBs must leave sufficient CPU processing bandwidth for baseline background communication (OB1) and terminal bus communications.

Engineer FAQ

What happens to variables modified by an interrupted OB?

Because the interrupted OB is simply paused in memory, variables written before the preemption retain their new values. However, if the higher-priority OB reads or writes the exact same global memory address (e.g., a shared DB address), data consistency issues can arise. PCS 7 CFC prevents this by enforcing strict block interconnection boundaries.

Why does PCS 7 assign higher priority numbers to slower OBs by default?

In standard STEP 7 hardware configurations, higher numerical priority corresponds to higher execution precedence. In PCS 7 default profiles, fast OBs (like OB35) are given appropriate priority so that fast PID loops can preempt slower supervisory tasks (like OB32), ensuring deterministic sampling jitter.

Can I measure the exact runtime of an individual CFC chart?

Yes. CFC provides runtime measurement capabilities in the Run Sequence editor. In addition, you can use system function SFC64 (TIME_TCK) or the APL block CountOh to measure elapsed execution microseconds between block entry and exit.