Using APL Blocks on S7-400H CPU 417-4HL04 and System Block Warnings

PCS 7 Advanced Process Library (APL) blocks are compatible with S7-400H CPU 417-4HL04 (6ES7417-4HL04-0AB0) at Firmware V4.0. However, during AS download, SIMATIC Manager displays the warning: 'Verification of used system blocks cannot be performed. This verification and AS download is user responsibility.' This warning occurs because Firmware V4.0 lacks the modern online system block interrogation API introduced in CPU Firmware V4.5. The CPU natively supports the required DPV1 system function blocks (SFB52 RDREC, SFB53 WRREC, SFB54 RALRM), so downloading under user responsibility is functional. Upgrading the CPU firmware to V4.5.x eliminates the warning and restores automated verification.

Root Cause of the System Block Verification Warning

When downloading a Continuous Function Chart (CFC) program containing PCS 7 Advanced Process Library (APL) blocks, the engineering system performs an automated pre-download validation. It queries the target CPU's operating system via online communication to verify that all System Function Blocks (SFBs) and System Functions (SFCs) referenced by the user program are supported by the installed firmware.

In legacy S7-400H controllers—specifically the CPU 417-4H revision 6ES7417-4HL04-0AB0 running Firmware V4.0.x (released in the PCS 7 V6.x era)—the operating system does not support the automated block descriptor query protocol implemented in modern PCS 7 engineering software (V7.1 SP1 through V9.x). Because CFC cannot interrogate the CPU's internal ROM catalog, it shifts responsibility to the engineer with the explicit warning:

'Die Überprüfung der verwendeten Systembausteine nicht durchgeführt werden kann (Anwenderverantwortung)'
(The verification of used system blocks cannot be performed. This verification and AS download is user responsibility.)

APL System Function Requirements on S7-400 Controllers

The Advanced Process Library relies heavily on standardized DPV1 communication and alarm mechanisms embedded in CPU ROM:

Acyclic Fieldbus Data Exchange: SFB52 (RDREC / Read Data Record) and SFB53 (WRREC / Write Data Record) are required for HART communication, driver diagnostics, and smart positioner parameters.
Interrupt Processing: SFB54 (RALRM / Receive Alarm) handles hardware interrupts and diagnostics from ET 200 distributed I/O stations.
Alarm Signalling: SFC107 (ALARM_DQ) and SFC108 (ALARM_DQC) generate process alarms with acknowledgment handling.
High-Precision Time Stamping: SFC64 (TIME_TCK) provides sub-millisecond execution timing.

Crucially, the S7-400H CPU 417-4H V4.0 does support these core SFBs and SFCs. Therefore, APL measuring points, motors, and valves execute correctly once downloaded, despite the warning dialogue.

Safe AS Download Procedure Under User Responsibility

Follow this engineering procedure to safely validate and download APL blocks to a CPU 417-4H V4.0 controller:

Verify Offline Block Utilization:
- In SIMATIC Manager, open the offline block folder of the S7 program.
- Confirm that standard SFBs (SFB52, SFB53, SFB54) present in the project originate from the standard S7 library compatible with S7-400.
Full Compilation:
- Open any CFC chart and execute Chart -> Compile -> Charts as Program -> Entire program.
- Verify that compilation completes with 0 Errors.
Execute AS Download:
- Select PLC -> Download.
- When the prompt 'Verification of used system blocks cannot be performed (user responsibility)' appears, review the listed SFBs/SFCs.
- Acknowledge the prompt to proceed with the download.
Post-Download Diagnostic Buffer Inspection:
- Open Target System -> Diagnostic Buffer in SIMATIC Manager.
- Verify that the CPU remains in RUN mode without transition to STOP and that no OB121 (programming error) or OB122 (I/O access error) events are logged.

S7-400H Firmware Compatibility and APL Support Matrix

The following table details APL support and verification behavior across S7-400H controller generations:

Controller GenerationManufacturer MLFBFirmware LevelAutomated System Block VerificationAPL Library CompatibilityRecommended ActionCPU 417-4H (Legacy)6ES7417-4HL04-0AB0FW V4.0.xNot Supported (Warning Issued)Supported (User Responsibility)Upgrade firmware to V4.5.x or accept warningCPU 417-4H (Upgraded)6ES7417-4HL04-0AB0FW V4.5.xFully Supported (No Warning)Fully SupportedFirmware update via memory cardCPU 417-5H (High End)6ES7417-5HT06-0AB0FW V6.0.xFully SupportedFully SupportedNone; native compatibilityCPU 410-5H Process Auto6ES7410-5HX08-0AB0FW V8.2+Fully SupportedOptimized for APLStandard controller for modern PCS 7

[!NOTE]
Commercial Accuracy Notice: Firmware upgrades on existing 6ES7417-4HL04-0AB0 hardware to Firmware V4.5 are software-only > updates delivered via memory card and do not require purchasing new controller hardware. When evaluating complete hardware > modernization to CPU 410-5H (6ES7410-5HX08-0AB0), distinguish controller hardware procurement, System Expansion Card > (SEC) capacity licenses, and AS RT Process Object licenses.

Verification

Confirm that APL blocks are executing reliably on the CPU 417-4H controller:

CFC Online Test: Open a CFC chart containing an APL block (such as MonAnL or MotL). Turn on Test -> Test Mode. Verify that live process values, feature bits, and status words update cyclically.
Diagnostic Buffer Check: Confirm that the CPU diagnostic buffer contains zero calls to OB121 (programming error). An OB121 call would occur if a required SFB was truly absent from CPU ROM.
WinCC Faceplate Control: Open the WinCC OS runtime and operate the motor or analog block icon. Confirm full faceplate interactivity and alarm generation.

Limitations and Operational Precautions

Keep the following operational limitations in mind when using APL on older S7-400 controllers:

Work Memory Limitations: APL blocks have significantly larger memory footprints (code and data) than classic Standard Library blocks. Monitor CPU work memory utilization in PLC -> Module Information -> Memory to avoid exhaustion.
Firmware Upgrade Considerations: Upgrading CPU 417-4H from V4.0 to V4.5 requires updating both redundant CPUs and necessitates an operating state transition (CPU STOP).
Avoid Mixing Libraries in Same Control Loop: Do not cascade classic standard library blocks directly into APL interlock structures without proper data type conversion (e.g. converting raw REAL/BOOL to APL structured data types).

Engineer FAQ

Will downloading APL blocks to a CPU 417-4H V4.0 cause the CPU to go into STOP?

No, provided the required SFBs (SFB52, SFB53, SFB54) are present in the CPU operating system. CPU 417-4H V4.0 includes these system functions in ROM, so the CPU remains in RUN.

Why did this warning only appear after adding APL blocks?

Classic PCS 7 Standard Library blocks relied on older system functions that were checked via legacy protocols. APL introduces extended DPV1 and alarm functions that trigger modern CFC verification mechanisms.

Can I upgrade CPU 417-4HL04 Firmware V4.0 to V4.5 online without stopping the plant?

No. S7-400H V4.x controllers do not support redundant bumpless firmware updates in RUN. A plant turnaround or planned outage is required.

Is CPU 417-4HL04 officially supported in PCS 7 V9.0?

No. PCS 7 V9.0 officially requires modern hardware baselines (such as CPU 410-5H or S7-400 V6+). While legacy hardware may operate in compatibility mode, Siemens recommends upgrading to CPU 410-5H.