C137 STEP 7
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Understanding STL RLO Termination, Timers, and Network Boundaries in Siemens STEP 7

In Siemens Statement List (STL), S5 timers, set/reset instructions, jump commands, and assignment coils (=) evaluate and terminate the current Result of Logic Operation (RLO). Writing multiple bit-logic checks without explicit assignment, network separation, or nesting parentheses causes the RLO from preceding checks to flow directly into downstream instructions, producing unintended timer triggers or unexpected output states.

Table of Contents

Technical Cause: How RLO Processing Works in STL

In Siemens SIMATIC S7-300, S7-400, and S7-1500 PLCs, the execution engine processes STL sequentially instruction by instruction. Every boolean evaluation (such as A, AN, O, or ON) modifies a internal status register bit known as the Result of Logic Operation (RLO).

Unintended execution logic occurs when developers assume that placing instructions on consecutive lines—or placing them in separate graphical networks within SIMATIC Manager or TIA Portal—automatically resets the RLO.

In STL:

  • The first bit-checking instruction (e.g., A I0.0) after a terminating instruction initializes a new logic chain (First Check / FC bit set to 0).
  • Timer instructions (such as SD T1), Set/Reset coils (S, R), and Output assignments (=) evaluate the active RLO bit at their point of execution.
  • Network boundaries do not automatically terminate the RLO. If Network 1 ends with an unassigned logic check (such as A I0.0), the resulting RLO carries directly into the top of Network 2 unless the First Check bit is reset by an explicit terminating statement.

Plaintext

Incorrect Continuous Stream:
  Network 1:
  A   I 0.0     \
  O   I 0.4      |--> Sets RLO bit in Status Word
  L   S5T#4S     |    Load instruction DOES NOT clear RLO!
  SD  T 1       /<--- Timer T1 evaluates active RLO (I0.0 OR I0.4)

  Correct Network Isolation:
  Network 1:
  A   I 0.0     \
  O   I 0.4      |--> Evaluates condition
  L   S5T#4S     |
  SD  T 1       /<--- Terminates Network 1 logic chain (Resets First Check bit)

  Network 2:
  A   T 1       <--- Starts a NEW logic chain (FC = 0)
  =   Q 0.0     <--- Assigns output independently

Prerequisites

To analyze and structure STL execution correctly, verify the following configuration requirements:

  • Engineering Environment: Siemens SIMATIC STEP 7 V5.x or TIA Portal (STEP 7 Professional).
  • Target Hardware: S7-300, S7-400, S7-1200 (SCL/LAD preferred), or S7-1500 controller.
  • Programming Knowledge: Familiarity with the S7 CPU Status Word registers (RLO, FC, STA, OR).

Evaluating Timer Logic and RLO Behavior in STL

Consider a single continuous code block attempting to evaluate a timer and a output bit:

Code snippet

A   I   0.0
O   A   I   0.4   // Syntax note: 'O A' combines AND/OR expressions
L   S5T#4S
SD  T   1
A   T   1
=   Q   0.0

When the CPU processes this sequence:

  1. A I 0.0 and O A I 0.4 evaluate the inputs and write the combined result into the RLO register.
  2. L S5T#4S loads a 16-bit time value into Accumulator 1. Load (L) and Transfer (T) instructions execute unconditionally and do not affect or depend on the RLO.
  3. SD T 1 (On-Delay Timer) reads the active RLO from step 1. If RLO = 1, timer T1 starts timing for 4 seconds. Executing SD terminates the preceding logical chain and resets the First Check (FC) bit to 0.
  4. A T 1 reads the status bit of timer T1. Because the previous logic chain was terminated by SD T 1, this line initializes a new first-check operation.
  5. = Q 0.0 assigns the state of T1 to output Q0.0.

The signal from I0.0 does not bypass the timer to drive Q0.0 directly because the timer call SD T1 acts as a logical boundary that consumes the preceding RLO before A T1 is evaluated.

Method 1: Structuring Logic Using Separate Networks

The standard practice for writing readable, maintainable STL code is to isolate discrete logical operations into individual networks and ensure every network ends with a terminating instruction.

Procedure

  1. Place the timer trigger conditions and timer execution block into Network 1.
  2. Terminate the network using the timer call (SD, SF, SS, SE, or SP).
  3. Place the timer output evaluation and output coil into Network 2.

Code snippet

// Network 1: Drive On-Delay Timer
A     I      0.0
O     I      0.4
L     S5T#4S
SD    T      1

// Network 2: Control Output Bit
A     T      1
=     Q      0.0

Expected result: Network 1 independently updates the timer state based on inputs I0.0 and I0.4. Network 2 evaluates the status of T1 independently and updates Q0.0.

Verification: In STEP 7 block monitoring mode, confirm that FC (First Check) displays 0 at line A T 1 in Network 2.

Method 2: Isolating Logic Branches Using Nesting Parentheses

When complex conditions must be processed within a single network, use nesting parentheses A( or O( to encapsulate sub-expressions and prevent RLO leakage across operations.

Procedure

Use nesting parentheses to group timer conditions separately from parallel bypass logic:

Code snippet

// Network 1: Nested Timer and Direct Output Logic
A(
A     I      0.0
O     I      0.4
L     S5T#4S
SD    T      1
A     T      1
)
O     I      0.2        // Direct bypass condition
=     Q      0.0

Automatic Ladder (LAD) Compatibility Format

If code must remain convertible between LAD and STL formats within TIA Portal or STEP 7 V5.x, include explicit NOP 0 placeholders generated during automatic LAD-to-STL compilation:

Code snippet

A(
A     I      0.0
O     I      0.4
L     S5T#4S
SD    T      1
A     T      1
)
NOP   0
NOP   0
NOP   0
=     Q      0.0

Expected result: The nesting scope insulates the internal evaluation steps. Output Q0.0 energizes if T1 completes its timing sequence OR if input I0.2 is TRUE.

Method 3: Controlling Execution Flow with Conditional Jumps

Because Load (L) and Transfer (T) instructions execute unconditionally regardless of the RLO state, use conditional jump instructions (JCN - Jump if RLO = 0) to skip register operations when conditions evaluate to FALSE.

Procedure

To prevent continuous overwriting of memory addresses during conditional processing, insert a jump label:

Code snippet

// Incorrect: MW12 is updated every scan cycle regardless of I0.0 status
A     I      0.0
L     MW     10
T     MW     12

// Correct: MW12 is updated ONLY when I0.0 is TRUE
A     I      0.0
JCN   m001        // Jump to label 'm001' if RLO = 0
L     MW     10
T     MW     12
m001: NOP    0    // Target label

Accumulator Retention Across Operations

In Siemens S7 CPUs, loading a value into Accumulator 1 shifts the previous contents into Accumulator 2. If no subsequent L instruction is executed, Accumulator 1 retains its value across sequential lines within the same block call.

This allows re-using loaded time or numeric values across multiple checks without executing redundant load statements:

Code snippet

// Load global timer duration once into Accumulator 1
L     S5T#4S

// Check First Trigger Condition using active Accumulator 1
A     I      0.0
SD    T      0

// Check Second Trigger Condition (Re-uses S5T#4S still in Accumulator 1)
A     I      0.1
SD    T      1

// Evaluate Outputs using Bitwise Exclusive-OR (XOR)
A     T      0
X     T      1
=     Q      0.0

Verification

To verify that RLO termination and logic chains execute as intended:

  1. Open the FC or FB in SIMATIC Manager or TIA Portal and activate Program Monitoring.

  2. Display the Status Word columns in the monitoring window:

    • RLO (Result of Logic Operation): Confirms the active boolean result passed to the next instruction.
    • FC (First Check Bit): Must transition to 0 after terminating instructions (=, S, R, SD, JCN), indicating that the following line starts a new evaluation context.
    • STA (Status Bit): Displays the raw boolean state of the referenced address.
      3. Force input bits and confirm that timer execution and coil assignments transition without unexpected carryover states from preceding networks.

Limitations and Operational Cautions

  • Cross-Network RLO Carryover: Ending a network with a bit evaluation (such as A I0.0) without an assignment coil (=) or terminating statement leaves FC = 1. The remaining RLO will combine unexpectedly with the first instruction of the next network.
  • Unconditional Execution of L and T: Placing L or T commands after a bit check (e.g., A I0.0 followed by L MW10) does not make the load operation conditional. The data transfers every scan cycle unless isolated by a jump instruction (JCN).
  • SCL and LAD Preferences: While STL provides precise register control on legacy S7-300/400 systems, modern S7-1200 and S7-1500 PLCs execute SCL (Structured Control Language) and LAD (Ladder Logic) significantly faster due to optimized CPU compiler architectures.

Engineer FAQ

Which STL instructions act as explicit RLO terminators?

Assignment coils (=), Set (S), Reset (R), Jump instructions (JCN, JMP), and all timer/counter execution calls (SD, SE, SF, SP, SS, CU, CD) reset the First Check (FC) bit to 0, terminating the current logic chain.

Why does my ladder program compile into STL code with NOP 0 instructions?

NOP 0 (No Operation) statements are automatically inserted by the STEP 7 compiler as structural placeholders to preserve graphical positioning and parameter alignment when converting Ladder (LAD) diagrams into Statement List (STL). They can be safely omitted in custom hand-written STL without changing logic execution.

Does a network boundary line in STEP 7 automatically reset the RLO bit?

No. Network divisions are visual organizational tools in the engineering interface. The CPU compiles STL sequentially, and RLO state carries across network boundaries unless explicitly terminated by an assignment or control instruction.

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